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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13712-4E
16-Bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90470 Series
MB90473/474/477/478/F474L/F474H
s DESCRIPTIONS
The FUJITSU MB90470 Series is a 16-bit general-purpose microcontroller designed for consumer products and other process control applications requiring high-speed and real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing. Peripheral resources built into the MB90470 series include 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit input-output timer, 8/16-bit up-counter, PWC timer, I2C*2 interface, DTP/external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd. *2 : I2C license : This product includes licensing of Philips I2C patents if used by the customer in an I2C system subject to the I2C standard specifications established by Philips.
s PACKAGES
100-pin plastic QFP 100-pin plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90470 Series
s FEATURES
* Clocks Minimum instruction execution time : 50.0 ns at 5 MHz base oscillation with 4 x multiplier (internal operation at 20 MHz/3.3 V 0.3 V) 62.5 ns at 4 MHz base oscillation with 4 x multiplier (internal operation at 16 MHz/3.0 V 0.3 V) Uses PLL clock multiplier. * Maximum memory size 16 Mbytes * Instruction set optimized for control applications Handles bit, byte, word, long-word data 23 standard addressing modes 32-bit accumulator for enhanced high-precision calculation Signed multiply-divide and expanded RETI instructions * Instruction system compatible with high-level language (C) multitasking System stack pointer Instruction set correlation and barrel shift instructions * Non-multi bus or multi-bus compatible * Program patch function (for two address pointers) * Improved execution speed 4-byte queue * Powerful interrupt functions 8 external interrupt functions with 8-level programmable priority * Data transfer functions (DMA or Extended intelligent I/O service) 16 channels maximum DMA maximum assured operation frequency : 16 MHz Extended intelligent I/O service maximum assured operation frequency : 20 MHz * Built-in ROM Flash versions : 256 KB, Mask ROM versions : 128 KB/256 KB * Built-in RAM 10 KB/16 KB * General purpose ports 84 ports maximum (includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting) * A/D converter RC sequential comparator type, 8 channels 10-bit resolution, conversion time 4.65 s (at 20 MHz operation) * I2C interface 1 channel * PG 1 channel * UART 1 channel * I/O expansion serial interface (SIO) 2 channels * 8/16-bit up/down timer 1 channel * 16-bit PWC 3 channels (including 2-channel input comparison function) (Continued)
2
MB90470 Series
(Continued) * 16-bit reload timer 1 channel (8-bit x 2-channel, 16-bit x 1-channel mode switching function provided) * 16-bit input-output timer 2-channel input capture, 6-channel output compare, 1-channel free run timer * 2 built-in clock generator systems * Low power modes Stop, sleep, CPU intermittent mode, watch mode, etc. * Package options QFP100/LQFP100 * Process CMOS technology * Supply voltage Can operate on 3 V single supply systems (with 5 V interface provided by some pins with 3/5 V dual-supply capability)
3
MB90470 Series
s PRODUCT LINEUP
Part number Parameter ROM capacity RAM capacity MB90F474L FLASH 256 KB 16 KB MB90F474H FLASH 256 KB 16 KB MB90473 MASKROM 128 KB 10 KB MB90474 MASKROM 256 KB 16 KB
CPU functions
Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time
: 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 62.5 ns (with 16 MHz machine clock)
Ports UART 8/16-bit PPG timer 8/16-bit up-down counter/timer 16-bit 16-bit free-run timer input/ Output compare (OCU) output timers Input capture (ICU) DTP/external interrupt circuit I/O expansion serial interface I C interface Time base timer
2
General purpose input/output ports : 84 Max General purpose input/output ports (CMOS output) General purpose input/output ports (built-in pull-up resistance) General purpose input/output ports (N-ch open drain) Stop-start synchronized : 1 channel 8-bit 6-channel/16-bit 3-channel Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers Channel : 1 Overflow interrupt Channels : 6 Pin input source : from compare register match signal Channels : 2 Register rewritten from pin input (rising/falling/both edges) External interrupt pins : 8 channels (set to edge or level correlation) 2-channel, built-in 1-channel, built-in 18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz) Conversion accuracy : 8/10-bit switchable Single conversion mode (converts selected channel 1 time only) Scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (converts selected channels continuously) Stop conversion mode (converts selected channel, stops and repeats) Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz) Sleep, stop, CPU intermittent, watch mode CMOS Flash model, low Flash model, high voltage version voltage version (f = 10 MHz or (f = 20 MHz) less at VCC = 2.4 V) Mask version Mask version
A/D converter
Watchdog timer Low power (standby) modes Process Notes Emulator dedicated power supply 4
(Continued)
MB90470 Series
(Continued)
Part number Parameter ROM capacity RAM capacity MB90477 MASKROM 256 KB 8 KB MB90478 MASKROM 256 KB 8 KB MB90V470B 16 KB : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 50 ns (with 20 MHz machine clock)
CPU functions
Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time
Ports
General purpose input/output ports : 84 Max General purpose input/output ports (CMOS output) General purpose input/output ports (built-in pull-up resistance) General purpose input/output ports (N-ch open drain) Stop-start synchronized : 1 channel 8-bit 6-channel/16-bit 3-channel Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers Channel : 1 Overflow interrupt Channels : 6 Pin input source : from compare register match signal Channels : 2 Register rewritten from pin input (rising/falling/both edges) External interrupt pins : 8 channels (set to edge or level correlation) 2-channel, built-in 1-channel, built-in 18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz) Conversion accuracy : 8/10-bit switchable Single conversion mode (converts selected channel 1 time only) Scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (converts selected channels continuously) Stop conversion mode (converts selected channel, stops and repeats) Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz) Sleep, stop, CPU intermittent, watch mode CMOS Mask version Mask version without I2C built-in interface EVA function User pin Included 5
UART 8/16-bit PPG timer 8/16-bit up-down counter/timer 16-bit free-run timer 16-bit input/ Output compare (OCU) output timers Input capture (ICU) DTP/external interrupt circuit I/O expansion serial interface I C interface Time base timer
2
A/D converter
Watchdog timer Low power (standby) modes Process Notes Emulator dedicated power supply
MB90470 Series
s PIN ASSIGNMENTS
(TOP VIEW)
P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
6
P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 VCC5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2
(FPT-100P-M06)
MB90470 Series
(TOP VIEW)
P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 VCC5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D13 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3
P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2
(FPT-100P-M05)
7
MB90470 Series
s PIN DESCRIPTION
Pin no. LQFP 80 81 78 77 75 QFP 82 83 80 79 77 Pin name X0 X1 X0A X1A RST P00 to P07 83 to 90 85 to 92 C (CMOS) Circuit type A A A A B Oscillator pin Oscillator pin 32 kHz oscillator pin 32 kHz oscillator pin Reset input pin General purpose input/output ports. Set the pull-up resistance setting register (RDR0) to add pull-up resistance (RD00-RD07 = "1" ) . (Not valid when set for output) In multiplex mode, these pins function as external address/ data bus lower input/output pins. In non-multiplex mode, these pins function as external data bus lower output pins. General purpose input/output ports. Set the pull-up resistance setting register (RDR1) to add pull-up resistance (RD10-RD17 = "1" ) . (Not valid when set for output) C (CMOS) In multiplex mode, these pins function as external address/ data bus higher input/output pins. In non-multiplex mode, these pins function as external data bus higher output pins. General purpose input/output ports. In external bus mode, pins for which the corresponding bit in the external address output control register (HACR) is "1" function as the general purpose input/output ports. E In multiplex mode, pins for which the corresponding bit in the (CMOS/H) external address output control register (HACR) is "0" function as the upper address output pins (A16 to A19) . In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is "0" function as the upper address output pins (A16 to A19) . General purpose input/output ports. In external bus mode, pins for which the corresponding bit in the external address output control register (HACR) is "1" function as the general purpose input/output ports. In multiplex mode, pins for which the corresponding bit in the E external address output control register (HACR) is "0" function (CMOS/H) as the upper address output pins (A20 to A23) . In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is "0" function as the upper address output pins (A20 to A23) . PPG timer output pins. Description
AD00 to AD07 D00 to D07
P10 to P17 91 to 98 93 to 100
AD08 to AD15 D08 to D15
P20 to P23 99 100 1 2
1 to 4
A16 to A19
A16 to A19
P24 to P27
3 to 6
5 to 8
A20 to A23
A20 to A23 PPG0 to PPG3 LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 8
(Continued)
MB90470 Series
Pin no. LQFP QFP Circuit type
Pin name P30
Description General purpose input/output port.
7
9
A00 AIN0 P31
E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch0) General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch0) General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch0) General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch1) General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch1) General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. 8/16-bit up-down timer input pin. (ch1) General purpose input/output ports. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. Functions as PWC input pin. General purpose input/output port. G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. Single serial I/O input pin General purpose input/output port. F (CMOS) In non-multibus bus mode, this pin functions as an external address pin. Single serial I/O output pin
8
10
A01 BIN0 P32
10
12
A02 ZIN0 P33
11
13
A03 AIN1 P34
12
14
A04 BIN1 P35
13
15
A05 ZIN1 P36, P37
14 15
16 17
A06, A07 PWC0, PWC1 P40
16
18
A08 SIN2 P41
17
19
A09 SOT2
(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 9
MB90470 Series
Pin no. LQFP QFP Circuit type
Pin name P42
Description General purpose input/output port.
18
20
A10 SCK2 P43, P44
G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. Single serial I/O clock input/output pin General purpose input/output ports. F (CMOS) In non-multibus bus mode, this pin functions as an external address pin. PG input pins General purpose input/output ports. G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. PG input pin General purpose input/output ports. F (CMOS) In non-multibus bus mode, this pin functions as an external address pin. Output compare event output pins D (CMOS) General purpose input/output port. In external bus mode, this pin functions as the ALE pin In external bus mode, this pin functions as the address load enable signal (ALE) pin General purpose input/output port. In external bus mode, this pin functions as the RD pin. In external bus mode, this pin functions as the read strobe output (RD) pin. General purpose input/output port. In external bus mode, this pin functions as the WRL pin when the WRE bit in the EPCR register is set to "1". In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port. General purpose input/output port. In external bus mode with 16-bit bus width, this pin functions as the WRH pin when the WRE bit in the EPCR register is set to "1". In external bus mode with 16-bit bus width, this pin functions as the higher data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port.
19 20
21 22
A11, A12 MT00, MT01 P45
22
24
A13 EXTC P46, P47
23 24
25 26
A14, A15 OUT4/OUT5 P50
68
70 ALE P51
69
71 RD
D (CMOS)
P52 70 72 WRL D (CMOS)
P53 71 73 WRH D (CMOS)
(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
10
MB90470 Series
Pin no. LQFP QFP Circuit type
Pin name
Description General purpose input/output port. In external bus mode, this pin functions as the HRQ pin when the HDE bit in the EPCR register is set to "1". In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port. General purpose input/output port. In external bus mode, this pin functions as the HAK pin when the HDE bit in the EPCR register is set to "1". In external bus mode, this pin functions as the hold acknowledge output (HAK) pin. When the HDE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port. General purpose input/output port. In external bus mode, this pin functions as the DRY pin when the RYE bit in the EPCR register is set to "1". In external bus mode, this pin functions as the external ready input (RDY) pin. When the RYE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port. General purpose input/output port. In external bus mode, this pin functions as the CLK pin when the CKE bit in the EPCR register is set to "1". In external bus mode, this pin functions as the machine cycle clock output (CLK) pin. When the CKE bit in the EPCR register is set to "0",this pin functions as a general purpose input/output port. General purpose input/output ports. Analog input pins. General purpose input/output ports. Analog input pins.
P54 72 74 HRQ D (CMOS)
P55 73 75 HAK D (CMOS)
P56 74 76 RDY D (CMOS)
P57 76 78 CLK P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P70 SIN0 P71 SOT0 P72 SCK0 P73 TIN0 P74 TOT0 D (CMOS)
36 to 39 38 to 41 41 to 44 43 to 46 25 26 27 28 29 27 28 29 30 31
H (CMOS) H (CMOS)
General purpose input/output port. G (CMOS/H) UART data input pin. F (CMOS) General purpose input/output port. UART data output pin.
General purpose input/output port. G (CMOS/H) UART clock input pin. General purpose input/output port. G (CMOS/H) 16-bit reload timer event input pin. F (CMOS) General purpose input/output port. 16-bit reload timer output pin.
(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 11
MB90470 Series
Pin no. LQFP 30 QFP 32 Circuit type
Pin name P75 PWC2 P76
Description
General purpose input/output port. G (CMOS/H) PWC input pin. General purpose input/output port. I 2 2 (NMOS/H) I C interface data input/output pin. During I C interface operation, the port output should be set to High-Z level. General purpose input/output port. I 2 2 (NMOS/H) I C interface clock input/output pin. During I C interface operation, the port output should be set to High-Z level. General purpose input/output ports. E (CMOS/H) External interrupt input pins. General purpose input/output ports. E (CMOS/H) External interrupt input pins. General purpose input/output port. E Single serial I/O data input pin. (CMOS/H) Chip select 0. General purpose input/output port. D (CMOS) Single serial I/O data output pin. Chip select 1. General purpose input/output port. E Single serial I/O clock input/output pin. (CMOS/H) Chip select 2. General purpose input/output port. E (CMOS/H) In A/D converter operation, this pin functions as the external trigger input pin. Chip select 3. D (CMOS) D (CMOS) General purpose input/output port. PPG timer output pin. General purpose input/output port. PPG timer output pin. In free run timer operation, this pin functions as the external clock input pin.
31
33
SCL P77
32 45 46
34 47 48
SDA P80, P81 IRQ0, IRQ1 P82 to P87 IRQ2 to IRQ7 P90 SIN1 CS0 P91
50 to 55 52 to 57
56
58
57
59
SOT1 CS1 P92
58
60
SCK1 CS2 P93 FRCK
59
61 ADTG CS3
60 61 62
62 63 64
P94 PPG4 P95 PPG5 P96 IN0
General purpose input/output port. E (CMOS/H) Functions as input capture ch 0 trigger input.
(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
12
MB90470 Series
(Continued) Pin no.
LQFP 63 QFP 65
Pin name P97 IN1 PA0 to PA3 OUT0 to OUT3 AVCC AVRH AVSS MD0 to MD2 VCC3 VCC5 VSS
Circuit type
Description
General purpose input/output port. E (CMOS/H) Functions as input capture ch 1 trigger input. D (CMOS) General purpose input/output ports. Output compare event output pins. A/D converter power supply pin. A/D converter external reference power pin. A/D converter power supply pin.
64 to 67 66 to 69 33 34 35 35 36 37
47 to 49 49 to 51 82 21 9 40 79 84 23 11 42 81
J Input pins for specifying operating mode. (CMOS/H) 3.3 V 0.3 V power supply pin (VCC3) . 3.3 V 0.3 V/5.0 V 0.5 V dual power supply pin (VCC5) . Power supply input pins (GND) .
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package Notes : * For use as a 3.3 V single supply device, apply the same voltage to the VCC3 and VCC5 power supply pins. * For use with a dual power supply, apply the respective voltages to the VCC3 and VCC5 power supply pins. * In use with a dual power supply, a total of 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/ A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5 and P70/SIN0 to P77/SDA) can be used in a 5 V interface. Note that all other pins must be used in 3 V interface. * In use with a dual power supply, it is not possible to turn on only the 5 V or the 3 V power supply independently. Always turn on both power supplies simultaneously. (It is recommended that the 3 V power to the MB90470 series be turned on first.)
13
MB90470 Series
s I/O CIRCUIT TYPES
Type Circuit Remarks
X1, X1A
A
X0, X0A
Oscillator feedback resistance : X1,X0 1 M approx. X1A,X0A 10 M approx. Includes standby control
Standby control signal
B
HYS
Hysteresis with pull-up resistance Input resistance 50 k approx.
CTL
C
Includes input pull-up resistance control CMOS level input/output Resistance : 50 k approx.
CMOS
D
CMOS
CMOS level input/output
E
CMOS
Hysteresis input CMOS level input/output
(Continued)
14
MB90470 Series
(Continued) Type
Circuit
Remarks
Open drain control signal
F
CMOS
CMOS level input/output Includes open drain control
Open drain control signal
G
HYS
CMOS level output Hysteresis input Includes open drain control
H
CMOS Analog input
CMOS level input/output Analog input
Digital output
I
HYS
Hysteresis input N-ch open drain output
(Flash model) Flash model CMOS level input Includes high voltage control for FLASH test
J
Spreading resistance
Control signal Mode input
(Mask version)
HYS
Mask version Hysteresis input port 15
MB90470 Series
s HANDLING DEVICES
(1) Strictly observe maximum rated voltages (prevent latchup) When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH) and analog input do not exceed the digital power supply (VCC) . (2) Treatment of unused pins If unused input pins are left open, abnormal operation or latchup may cause permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 k. Also any unused input/output pins should be left open in output status, or if set to input status should be treated in the same way as input pins. (3) Precautions for use of external clock signals Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used 20 MHz should be used as a guideline for an upper frequency limit. The following figure shows a sample use of external clock signals.
X0
OPEN
X1
(4) Power supply pins When using multiple VCC/VSS sources, always make sure to design devices with external connections of all power supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 F be connected between VCC and VSS as close to the pins as possible. (5) Crystal oscillator circuits Abnormal operation of this device can result from noise in the proximity of the X0/X1 and X0A/X1A pins. For stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close as possible between the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) as well as ground, and be wired so as to avoid crossing other wiring wherever possible.
16
MB90470 Series
(6) Precautions for use of external oscillators (crystals) The target value for the upper limit of oscillator (crystals) frequencies should be 20 MHz. Also, when operating at internal frequencies of 16 MHz, the PLL multiplier should be used. (7) Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. Note : VCC = VCC3 = VCC5 (8) Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = AVRH = VCC, and AVSS = VSS. (9) Power-on procedures In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise during power-on should be attained within 50 s (0.2 V to 2.7 V) . (10) Stable power supply Even within the operating range of the VCC supply voltage, rapid changes in supply voltage may cause abnormal operation. As a basis for stable operation, it is recommended that voltage variation be restricted in order to limit VCC ripple fluctuations (P-P values) to 10% at commercial frequencies of 50 Hz to 60 Hz, and transient fluctuations to 0.1 V/ms at instantaneous points such as power switching. (11) Precautions for use of two power supplies The MB90470 series usually uses the 3-V power supply as the main power source. With VCC3 = 3 V and VCC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5, P70/SIN0 to P77/SDA for the 5-V power supply separetely from the 3-V power supply at all operation mode. (Caution) The analog power supply for the A/D converter (AVCC, AVSS etc.) can only operate with the 3 V system. (12) Crystal oscillator circuits during power-saving operation When the power supply is lower than 2.0 V, the external crystal oscillator may not operate even when power is on. For this reason, the use of an external clock signal is recommended. (13) Caution : low-voltage flash models (2.4 V to 3.6 V/10 MHz) do not have security functions (14) Treatment of unused input pins N.C. (internally connected) pins should always be left open. (15) When the dual-supply MB90470 series is used as a 1-supply device, use connections so that X0A = VSS, and X1A = Open.
17
MB90470 Series
(16) For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V. (17) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
18
MB90470 Series
s BLOCK DIAGRAM
CPU FMC-16LX series core Interrupt controller PPG0, PPG1 PPG2, PPG3 PPG4, PPG5 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 EXTC MT00 MT01 CS0, CS1, CS2, CS3
X0, X1, RST X0A, X1A MD2, MD1, MD0
8
Clock control circuit RAM
ROM
8/16-bit PPG
DMA 8/16-bit up/down counter Communication prescaler 2 PG
F2MC-16LX BUS
SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7
UART
Chip select
I/O expansion serial interface x 2 channels
Input/output timer 16-bit input capture x 2 16-bit output compare x 6 16-bit free-run timer IN0, IN1 OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 TIN0 TOT0 SCL SDA 8 IRQ0 to IRQ7
A/D converter (10-bit)
16-bit reload timer
PWC0 PWC1 PWC2
I2C interface 16-bit PWC 3 channels External interrupt
I/O ports 8 P00 P07 8 P10 P17 8 P20 P27 8 P30 P37 8 P40 P47 8 P50 P57 8 P60 P67 8 P70 P77 8 P80 P87 8 P90 P97 4 PA0 PA3
P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P75 (6 pins) P76, P77 (2 pins)
: Input pull-up resistance setting register provided. : Input pull-up resistance setting register provided. : Open drain setting register provided. : Open drain setting register provided. : Open drain
Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However pins may not be used as I/O ports when they are in use as pins for build-in function modules.
19
MB90470 Series
s MEMORY MAP
Single chip FFFFFFH Internal ROM external bus External ROM external bus
ROM area Address 1#
ROM area
010000H ROM area FF bank image 004000H ROM area FF bank image
*
Address 2#
RAM 000100H 0000D0H
Register
RAM
Register
RAM
Register
Peripheral 000000H : Internal
Peripheral
Peripheral
: External
: Access not available
* : In models where address 2# coincides with 004000H, there is no external area.
Model MB90473 MB90474 MB90477/478 MB90F474 MB90V470 Address 1# FE0000H FC0000H FC0000H FC0000H (FC0000H) Address 2# 002900H 004000H 002100H 004000H 004000H
The image of FF bank ROM is reflected in the top of the 00 bank, for greater efficiency in using the C compiler for small models. The lower 16-bit address on the FF bank is the same as the lower 16-bit address on the 00 bank, so that it is possible to reference tables in ROM without using the pointer for a far specification. For example, when accessing 00C000H, it is actually the content of ROM at FFC000H that is accessed. Here, because the ROM area on the FF bank exceeds 48 KB, it is not possible to view the entire area in the image on the 00 bank. Therefore, the image from FF4000H to FFFFFFH is visible on the 00 bank, and FF0000H to FF3FFFH is visible only on the FF bank. 20
MB90470 Series
s F2MC-16L CPU PROGRAMMING MODEL
* Special purpose registers
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General purpose registers
MSB 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16 bit LSB
* Processor status
15 PS ILM 13 12 RP 87 CCR 0
21
MB90470 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port 3 timer input enable register Interrupt/DTP enable register Interrupt/DTP enable register Demand level setting register Demand level setting register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 pin register Port 0 resistance register Port 1 resistance register Port 7 pin register Analog input enable register Symbol PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA UDRE ENIR EIRR ELVR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 ODR7 ADER Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (OD control) Port 0 (pull-up) Port 1 (pull-up) Port 7 (OD control) Port 5, A/D DTP/external interrupt Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Up/down timer input control Default XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1 1XXXXXX XXXXXXXX XXXXXXXX - - - - XXXX XX 0 0 0 0 0 0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 --000000 00000000 00000000 ----0000 00000000 00000000 00000000 --000000 11111111
(Continued)
22
MB90470 Series
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H Clock divider control register Serial mode control status register 0 Serial mode control status register 0 Serial data register Clock divider control register Serial mode control status register 1 Serial mode control status register 1 Serial data register Clock divider control register PPG reload register L (ch0) PPG reload register H (ch0) PPG reload register L (ch1) PPG reload register H (ch1) PPG reload register L (ch2) PPG reload register H (ch2) PPG reload register L (ch3) PPG reload register H (ch3) PPG reload register L (ch4) PPG reload register H (ch4) PPG reload register L (ch5) PPG reload register H (ch5) PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register PPG4 operating mode control register PPG5 operating mode control register PPG0, 1 output control register Register name Serial mode register 0 Serial control register 0 Serial input register/ serial output register Serial status register Symbol SMR0 SCR0 SIDR/ SODR0 SSR0 Access R/W R/W R/W R/W Communication prescaler (UART) SCI1 (ch0) Communication prescaler (SCI0) SCI2 (ch1) Communication prescaler (SCI1) UART0 Resource name Default 00000X00 00000100 XXXXXXXX 00001000
Reserved CDCR SMCS0 SMCS0 SDR0 SDCR0 SMCS1 SMCS1 SDR1 SDCR1 PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PPGC0 PPGC1 PPGC2 PPGC3 PPGC4 PPGC5 PPG01 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG 8/16-bit PPG (ch0-ch5) 00--0000 ----0000 00000010 XXXXXXXX 0---0000 ----0000 00000010 XXXXXXXX 0---0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0 X 0 0 0XX 1 0X000001 0 X 0 0 0XX 1 0X000001 0 X 0 0 0XX 1 0X000001 00000000
(Continued)
23
MB90470 Series
Address 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H Control status register Data register Output compare register (ch0) low Output compare register (ch0) high Output compare register (ch1) low Output compare register (ch1) high Output compare register (ch2) low Output compare register (ch2) high Output compare register (ch3) low Output compare register (ch3) high Output compare register (ch4) low Output compare register (ch4) high Output compare register (ch5) low Output compare register (ch5) high Output compare control register (ch0) Output compare control register (ch1) Output compare control register (ch2) Output compare control register (ch3) Output compare control register (ch4) Output compare control register (ch5) Input capture register (ch0) low Input capture register (ch0) high Input capture register (ch1) low Input capture register (ch1) high Input capture control register PPG4, 5 output control register PPG2, 3 output control register Register name Symbol PPG23 PPG45 ADCS1 ADCS2 ADCR1 ADCR2 OCCP0 OCCP1 OCCP2 OCCP3 OCCP4 OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 IPCP0 IPCP1 ICS01 Access R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W 16-bit output timer Input capture (ch0, 1) 16-bit output timer OCU (ch4, 5) 16-bit output timer output compare (ch0-ch5) A/D converter Resource name 8/16-bit PPG 8/16-bit PPG Default 00000000 00000000 00000000 00000000 XXXXXXXX 0 0 0 0 0 XXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000--00 ---00000 0000--00 ---00000 0000--00 ---00000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000
Reserved Reserved Reserved
Reserved
(Continued)
24
MB90470 Series
Address 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H PWC1 division ratio register PWC0 control status register PWC0 data buffer register PWC1 control status register PWC1 data buffer register PWC2 control status register PWC2 data buffer register PWC0 division ratio register Count status register ch1 ROM mirror function select register Counter control register low ch1 Counter control register high ch1 Count status register ch0 Register name Timer data register low Timer data register high Timer control status register Timer control status register Compare clear register low Compare clear register high Up down count register ch0 Up down count register ch1 Reload compare register ch0 Reload compare register ch1 Counter control register low ch0 Counter control register high ch0 Symbol TCDT TCDT TCCS TCCS CPCLR UDCR0 UDCR1 RCR0 RCR1 CCRL0 CCRH0 ROMM CCRL1 CCRH1 CSR0 CSR1 Access R/W R/W R/W R/W R/W R R W W R/W R/W W R/W R/W R/W R/W 8/16-bit UDC 8/16-bit up-down timer-counter ROM mirror function 8/16-bit up-down timer-counter 16-bit output timer Free run timer Resource name Default 00000000 00000000 00000000 0--00000 XXXXXXXX XXXXXXXX 00000000 00000000 00000000 00000000 0X00X000 00000000 -------1 0X00X000 -0000000 00000000 00000000 00000000 16-bit PWC timer (ch0) PWCR0 PWCSR1 PWCR1 PWCSR2 PWCR2 DIVR0 DIVR1 R/W R/W 16-bit PWC timer (ch1) R/W R/W 16-bit PWC timer (ch2) R/W R/W R/W PWC (ch0) PWC (ch1) 0000000X 00000000 00000000 00000000 0000000X 00000000 00000000 00000000 0000000X 00000000 00000000 ------00 ------00
Reserved
Reserved Reserved PWCSR0 R/W
Reserved Reserved
(Continued)
25
MB90470 Series
Address 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH to 9BH 9CH 9DH 9EH 9FH A0H A1H A2H, A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 DMA control register DMA control register Flash memory control status register DMA stop status register Auto ready function select register External address output control register Bus control signal control register Watchdog control register Time base timer control register Watch timer control register DMA status register DMA status register Program address detection control status resister Delay interrupt source generate/ release register Low power mode register Clock select register PG control register I2C bus status register I C bus control register I C bus clock select register I2C bus address register I2C bus data register
2 2
Register name PWC2 division ratio register
Symbol DIVR2 IBSR IBCR ICCR IADR IDAR PGCSR DSRL DSRH PACSR DIRR LPMCR CKSCR DSSR ARSR HACR EPCR WDTC TBTC WTC DERL DERH FMCR
Access R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W R/W R/W R/W R/W R/W R/W
Resource name PWC (ch2)
Default ------00 00000000 00000000
Reserved
I C functions
2
- - 0XXXXX - XXXXXXX XXXXXXXX
Reserved PG DMA DMA Address Match Detection Function Delay interrupt generator module Low power modes Low power modes DMA External pins External pins External pins Watchdog timer Time base timer Watch timer DMA DMA Flash memory interface 00000--00000000 00000000 00000000 --------0 00011000 11111100 00000000 0011--00 00000000 1000*10XXXXX 1 1 1 1XX00100 10001000 00000000 00000000 000X0000 Prohibited
Reserved
Reserved
Prohibited ICR00 ICR01 ICR02 ICR03 R/W R/W R/W R/W XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1
(Continued)
26
MB90470 Series
Address B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH, CFH D0H to FFH 100H to #H 1FF0 1FF1 1FF2
Register name Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Chip select MASK register 0 Chip select area register 0 Chip select MASK register 1 Chip select area register 1 Chip select MASK register 2 Chip select area register 2 Chip select MASK register 3 Chip select area register 3 Chip select control register Chip select control active level register Timer control status registers 16-bit timer register 16-bit reload register
Symbol ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 CMR0 CAR0 CMR1 CAR1 CMR2 CAR2 CMR3 CAR3 CSCR CALR TMCSR TMR/ TMRLR
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Default XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 XXXX 0 1 1 1 11111111 00001111 11111111 00001111 11111111 00001111 11111111 ----000* ----0000 00000000 ----0000 XXXXXXXX
Chip select functions 0 0 0 0 1 1 1 1
16-bit reload timer R/W
Reserved External area RAM area Program address detection resister0 (Low order address) Program address detection resister0 (Middle order address) Program address detection resister0 (High order address) PADR0 R/W Address Match Detection Function XXXXXXXX
(Continued)
27
MB90470 Series
(Continued) Address
1FF3 1FF4 1FF5
Register name Program address detection resister1 (Low order address) Program address detection resister1 (Middle order address) Program address detection resister1 (High order address)
Symbol
Access
Resource name
Default
PADR1
R/W
Address Match Detection Function
XXXXXXXX
Interrupt symbols : R/W : Read/write enabled R : Read only W : Write only Default value symbols : 0 : This bit initialized to "0" 1 : This bit initialized to "1" * : This bit initialized to "0" or "1" X : Default value undefined - : This bit is not used.
28
MB90470 Series
s INTERRUPT SOURCES, INTERRUPT VECTORS & INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 PWC1 PWC2 PWC0 PPG0/PPG1 counter borrow PPG2/PPG3 counter borrow PPG4/PPG5 counter borrow 8/16-bit up/down counter timer compare/ underflow /overflow/ amp down inversion (ch0, 1) Input capture (ch0) load Input capture (ch1) load Output compare (ch0) match Output compare (ch1) match Output compare (ch2) match Output compare (ch3) match Output compare (ch4) match Output compare (ch5) match UART send end 16-bit free run timer/ 16-bit reload timer overflow UART receive end EI2OS DMA support channel no. 0 x x x x x x x x x 1 2 3 4 x 5 6 8 9 10 x x x 11 12 7 Interrupt vector No. #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH Interrupt control register No. ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H
#25
FFFF98H
ICR07
0000B7H
#26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36
FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH ICR08 ICR09 ICR10 ICR11 0000B8H 0000B9H 0000BAH 0000BBH
ICR12
0000BCH
(Continued)
29
MB90470 Series
(Continued)
Interrupt source SIO1 SIO2 I2C interface A/D Flash write/erase, time base timer, watch timer* Delay interrupt generator module x x x EI2OS DMA support channel no. 13 14 x 15 x x Interrupt vector No. #37 #38 #39 #40 #41 #42 Address FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register No. ICR13 ICR14 Address 0000BDH 0000BEH
ICR15
0000BFH
: Interrupt request flag cleared by the interrupt clear signal. The stop request is available. : Interrupt request flag cleared by the interrupt clear signal. x : Interrupt request flag not cleared by the interrupt clear signal. * : Note that flash write/erase cannot be used at the same time as the time base timer or watch timer. Note : * If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt request flags at the EI2OS/DMAC interrupt clear signal. Thus when EI2OS/DMA function of two sources is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding resource should be set to "0" for software polling processing. * Maximum assured operation frequency of DMA is 16 MHz.
30
MB90470 Series
s PERIPHERAL RESOURCES
1. I/O Ports
The I/O ports output data from the CPU to the I/O pins, and also load signals input at the I/O pins into the CPU, according to the port register (PDR) . The ports can also control the input/output direction of the I/O pins in bit units according to the port direction register (DDR) . The MB90470 series has 82 input/output pins and two open drain output pins. Ports 0 through A are input/output ports, and port 76, and 77 are the open drain ports. (1) Port Registers PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H PDRA Address : 00000AH
7 P07 7 P17 7 P27 7 P37 7 P47 7 P57 7 P67 7 P77 7 P87 7 P97 7 6 P06 6 P16 6 P26 6 P36 6 P46 6 P56 6 P66 6 P76 6 P86 6 P96 6 5 P05 5 P15 5 P25 5 P35 5 P45 5 P55 5 P65 5 P75 5 P85 5 P95 5 4 P04 4 P14 4 P24 4 P34 4 P44 4 P54 4 P64 4 P74 4 P84 4 P94 4 3 P03 3 P13 3 P23 3 P33 3 P43 3 P53 3 P63 3 P73 3 P83 3 P93 3 PA3 2 P02 2 P12 2 P22 2 P32 2 P42 2 P52 2 P62 2 P72 2 P82 2 P92 2 PA2 1 P01 1 P11 1 P21 1 P31 1 P41 1 P51 1 P61 1 P71 1 P81 1 P91 1 PA1 0 P00 0 P10 0 P20 0 P30 0 P40 0 P50 0 P60 0 P70 0 P80 0 P90 0 PA0
Default value Undefined
Access R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
11XXXXXX
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
* : Input/output port read/write operations are somewhat different than reading and writing to memory, and operate as follows. *Input mode Read : Reads the signal level of the corresponding pin. Write : Writes to the output latch. *Output mode Read : Reads the value of the data register latch. Write : Value is output to the corresponding pin. 31
MB90470 Series
(2) Port Direction Registers DDR0 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH
7 D07 7 D17 7 D27 7 D37 7 D47 7 D57 7 D67 7 7 D87 7 D97 7 6 D06 6 D16 6 D26 6 D36 6 D46 6 D56 6 D66 6 6 D86 6 D96 6 5 D05 5 D15 5 D25 5 D35 5 D45 5 D55 5 D65 5 D75 5 D85 5 D95 5 4 D04 4 D14 4 D24 4 D34 4 D44 4 D54 4 D64 4 D74 4 D84 4 D94 4 3 D03 3 D13 3 D23 3 D33 3 D43 3 D53 3 D63 3 D73 3 D83 3 D93 3 DA3 2 D02 2 D12 2 D22 2 D32 2 D42 2 D52 2 D62 2 D72 2 D82 2 D92 2 DA2 1 D01 1 D11 1 D21 1 D31 1 D41 1 D51 1 D61 1 D71 1 D81 1 D91 1 DA1 0 D 00 0 D10 0 D20 0 D30 0 D40 0 D50 0 D60 0 D70 0 D80 0 D90 0 DA0
Default value 00000000
Access R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
- - - - 0000
R/W
* When a pin is functioning as a port, the corresponding pin control setting is as follows : 0 : Input mode 1 : Output mode The register value is "0" at reset. * Port 76, 77 These ports do not have DDR registers. Data at these pins is always valid, so that when P76, P77 are used as I2C pins the PDR value should be "1". (The I2C functions should be stopped, when these pins are used as P76,P77 .) These ports have open drain configuration. If they are used as input ports, the output transistor is turned off, so that the output data register must be set to "1" and pull-up resistance applied. Note : If these registers are accessed using read-modify-write instructions (such as bit set instructions) ,the bit that is the object of the instruction will be set to the specified value but for other bits the value of the corresponding output register will be rewritten to the input value of the pin at that time. For this reason when a pin used for input is switched to output, first write the desired value to the PDR register, then set the DDR register to switch the pin direction. 32
MB90470 Series
(3) Input Resistance Registers RDR0 Address : 00001CH RDR1 Address : 00001DH
7 RD07 7 RD17 6 RD06 6 RD16 5 RD05 5 RD15 4 RD04 4 RD14 3 RD03 3 RD13 2 RD02 2 RD12 1 RD01 1 RD11 0 RD00 0 RD10
Default value 00000000
Access R/W
00000000
R/W
These registers control pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : Pull-up resistance applied in input mode. In output mode, the setting has no significance (no pull-up resistance) . The direction registers (DDR) control switching between input and output modes. In stop mode (SPL = 1) pull-up resistance is removed (high impedance) . When an external bus is used, this function is prohibited and no values should be written to this register. (4) Output Pin Registers ODR7 Address : 00001EH ODR4 Address : 00001BH
7 7 OD47 6 6 OD46 5 OD75 5 OD45 4 OD74 4 OD44 3 OD73 3 OD43 2 OD72 2 OD42 1 OD71 1 OD41 0 OD70 0 OD40
Default value 00000000
Access R/W
00000000
R/W
These registers control open drain operation in output mode. 0 : Operates as standard output port in output mode. 1 : Operates as open drain port in output mode. In input mode, the setting has no significance (High-Z output) . The direction registers (DDR) control switching between input and output modes. When an external bus is used, this function is prohibited and no values should be written to this register. (5) Analog Input Enable Register ADER Address : 00001FH
7 ADE7 6 ADE6 5 ADE5 4 ADE4 3 ADE3 2 ADE2 1 ADE1 0 ADE0
Default value 11111111
Access R/W
This register controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The register value is "1" at reset. (6) Up-down Timer Input Enable Mode UDER Address : 00000BH
7 6 5 UDE5 4 UDE4 3 UDE3 2 UDE2 1 UDE1 0 UDE0
Default value XX000000
Access R/W
This register controls the port 3 pins as follows. 0 : Port input mode 1 : Up-down timer input mode. The register value is "0" at reset. In the MB90470 series, the pin functions are as follows : UDE0 : P30/AIN0, UDE1 : P31/BIN0, UDE2 : P32/ ZIN0, UDE3 : P33/AIN1, UDE4 : P34/BIN1, UDE5 : P35/ZIN1 33
MB90470 Series
2. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication or CLK synchronized communication. * Full duplex double buffer * Asynchronous (start-stop synchronized) and CLK synchronized (no start bit or stop bit) operation * Supports multi-processor modes * Built-in dedicated baud rate generator Asynchronous operation : 76923/38461/19230/9615/500 K/250 Kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 K * Baud rate can be set independently from external clock * Can use internal clock feed from PPG1. * Data length : 7 bits (asynchronous normal mode only) or 8 bits * Master-slave communication functions (in multi-processor mode) : allows 1 (master) -to-n (slave) communications * Error detection functions (parity, framing, overrun) * NRZ-encoded transfer signal * DMAC support (receiving/sending)
34
MB90470 Series
(1) Register List
15 CDCR SCR SSR 8 bit 87 SMR SIDR (R)/SODR (W) 8 bit 0
Serial mode register (SMR)
7 6 MD0 (R/W) (0) 5 CS2 (R/W) (0) 4 CS1 (R/W) (0) 3 CS0 (R/W) (0) 2 1 0 SOE (R/W) (0)
Address : 000020H
MD1 (R/W) (0)
Reserved SCKE
(R/W) (X)
(R/W) (0)
Default value
Serial control register (SCR)
15 14 P (R/W) (0) 13 SBL (R/W) (0) 12 CL (R/W) (0) 11 A/D (R/W) (0) 10 REC (W) (1) 9 RXE (R/W) (0) 8 TXE (R/W) (0)
Address : 000021H
PEN (R/W) (0)
Default value
Serial input/output register (SIDR/SODR)
7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X)
Address : 000022H
D7 (R/W) (X)
Default value
Serial data register (SSR)
15 14 ORE (R) (0) 13 FRE (R) (0) 12 RDRF (R) (0) 11 TDRE (R) (1) 10 BDS (R/W) (0) 9 RIE (R/W) (0) 8 TIE (R/W) (0)
Address : 000023H
PE (R) (0)
Default value
Communication prescaler control register (CDCR)
15 14 SRST (R/W) (0) 13 () () 12 () () 11 DIV3 (R/W) (0) 10 DIV2 (R/W) (0) 9 DIV1 (R/W) (0) 8 DIV0 (R/W) (0)
Address : 000025H
MD (R/W) (0)
Default value
35
MB90470 Series
(2) Block Diagram
Control signal Receiving interrupt (to CPU) Dedicated baud rate generator PPG1 (internal connection) External clock Receiving control circuits SIN0 Start bit detect circuit Receiving bit counter Receiving parity counter Sending control circuits Send start circuit Sending bit counter Sending parity counter Clock select circuit RX clock TX clock SCK0 Sending interrupt (to CPU)
SOT0
Receiving status judgement circuit
Receiving shifter Receiving control circuit SIDR
Sending shifter Sending control circuit SODR
DMAC receiving error transmission signal (to CPU)
F2MC-16LX BUS
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC REX TXE
SSR register
PE ORE FRE RDRF TDRE BDS RIE TIE
Control signal
36
MB90470 Series
3. Expanded I/O Serial Interface
The expended I/O serial interface is a serial I/O interface in 8-bit x 1 channel configuration allowing clock synchronized data transmission. The interface has two serial I/O operating modes. * Internal shift clock mode : Data transfer is synchronized with an internal clock. * External shift clock mode : Data transfer is synchronized with a clock input from an external pin (SCK) . This mode allows the external clock pin (SCK) to be shared with a general purpose port that can transfer data according to CPU instructions. (1) Register List Serial mode control status register (SMCS)
15 14 SMD1 (R/W) 6 () 13 SMD0 (R/W) 5 () 12 SIE (R/W) 4 () 11 SIR (R/W) 3 MODE (R/W) 10 BUSY (R/W) 2 BDS (R/W) 9 STOP (R/W) 1 SOE (R/W) 8 STRT (R/W) 0 SCOE (R/W)
Initial value 0 0 0 0 0 0 1 0B Initial value - - - - 0 0 0 0B
Address :
000027H 00002BH
SMD2 (R/W) 7
Address :
000026H 00002AH
()
Serial data register (SDR)
7 6 D6 (R/W) 5 D5 (R/W) 4 D4 (R/W) 3 D3 (R/W) 2 D2 (R/W) 1 D1 (R/W) 0 D0 (R/W)
Initial value XXXXXXXXB
Address :
000028H 00002CH
D7 (R/W)
Communication prescaler control register (SDCR0, SDCR1) 000029H Address : 00002DH
15 MD (R/W) 14 () 13 () 12 () 11 DIV3 (R/W) 10 DIV2 (R/W) 9 DIV1 (R/W) 8 DIV0 (R/W)
Initial value 0 - - - 0000B
37
MB90470 Series
(2) Block Diagram
Internal data bus (MSB first) D0 to D7 SIN1, 2 SDR (Serial data register) SOT1, 2 Read Write D7 to D0 (LSB first) Select transfer direction Default value
SCK1, 2 Control circuit Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus SOE SCOE
SMD2 SMD1 SMD0
38
MB90470 Series
4. 8/10-bit A/D Converter
The A/D converter converts analog input voltages into digital values, and provides the following features : * Conversion time : minimum 4.9 s per channel (at 98 machine cycles/machine clock 20 MHz, including sampling time) * Sampling time : minimum 3.0 s per channel (at 60 machine cycles/machine clock 20 MHz) * Uses RC sequential comparison conversion with sample & hold circuit. * Selection of 8- or 10-bit resolution * Analog input from 8 channels, by program selection Single conversion mode : Convert 1 selected channel Scan conversion mode : Convert multiple consecutive channels. Select up to 8 channels by program selection. Continuous conversion mode : Convert specified channel continuously. Stop conversion mode : Convert one channel, pause and stand by until the next start. (Simultaneous conversion start available.) * At the end of A/D conversion, an A/D conversion end interrupt request can be sent to the CPU. This interrupt request can start the DMA and transfer the conversion data to memory, making it ideal for continuous processing. * Start sources include selection of software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status registers) ADCS1 Address : 000046H
7 MD1 0 R/W 6 MD0 0 R/W 5 ANS2 0 R/W 4 ANS1 0 R/W 3 ANS0 0 R/W 2 ANE2 0 R/W 1 ANE1 0 R/W 0 ANE0 0 R/W
Default value Bit attributes
ADCS2 bit Address : 000047H
15 BUSY 0 R/W
14 INT 0 R/W
13 INTE 0 R/W
12 PAUS 0 R/W
11 STS1 0 R/W
10 STS0 0 R/W
9 STRT 0 W
8
Reserved
0 R/W
Default value Bit attributes
ADCR2, ADCR1 (Data registers) ADCR1 bit Address : 000048H
7 D7 X R 6 D6 X R 14 ST1 0 W 5 D5 X R 13 ST0 0 W 4 D4 X R 12 CT1 0 W 3 D3 X R 11 CT0 0 W 2 D2 X R 10 X R 1 D1 X R 9 D9 X R 0 D0 X R 8 D8 X R
Default value Bit attributes
ADCR2 bit Address : 000049H
15 S10 0 R/W
Default value Bit attributes
39
MB90470 Series
(2) Block Diagram
AVCC AVRH AVSS D/A converter MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Sequential comparison register Comparator Data bus Data register ADCR1, ADCR2 A/D control register 1 A/D control register 2 ADCS1, ADCS2 Operating clock Prescaler
Sample & hold circuit
ADTG
Trigger start Timer start
Timer (PPG1 output)
40
Decoder
MB90470 Series
5. 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output in the form of a pulse for timer operation. The hardware configuration includes six 8-bit down counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins, and six interrupt outputs. The MB90470 provides six 8-bit PPG channels, which can also operate as three 16-bit PPG channels in the combination PPG0 + PPG1, PPG2 + PPG3, PPG4 + PPG5. The following is an overview of the functions of the PPG. * Six-channel independent 8-bit PPG output mode : Provides PPG output operation independently on six channels. * 16-bit PPG output operation mode : Provides 16-bit PPG output operation on three channels, using the combination PPG0 + PPG1, PPG2 + PPG3, PPG4 + PPG5. * 8 + 8-bit PPG output operation mode : Uses the PPG0 (PPG2/PPG4) output as the PPG1 (PPG3/PPG5) clock input, to enable 8-bit PPG output with any desired period. * PPG output operation : Outputs pulse waves at a specified period and duty ratio. Can be also used with an external circuit as a D/A converter.
41
MB90470 Series
(1) Register List PPGC0 (PPG0/2/4 operating mode control register) 00003AH 00003CH 00003EH
7 PEN0 (R/W) (0) 6 () (X) 5 PE00 (R/W) (0) 4 PIE0 (R/W) (0) 3 PUF0 (R/W) (0) 2 () (X) 1 () (X) 0
Reserved
() (1)
Read/write Default value
PPGC1 (PPG1/3/5 operating mode control register) 00003BH 00003DH 00003FH
15 PEN1 (R/W) (0) 14 () (X) 13 PE10 (R/W) (0) 12 PIE1 (R/W) (0) 11 PUF1 (R/W) (0) 10 MD1 (R/W) (0) 9 MD0 (R/W) (0) 8
Reserved
() (1)
Read/write Default value
PPG01/PPG23/PPG45 (PPG0-PPG5 output control register) 000040H 000042H 000044H
7 PCS2 (R/W) (0) 6 PCS1 (R/W) (0) 5 PCS0 (R/W) (0) 4 PCM2 (R/W) (0) 3 PCM1 (R/W) (0) 2 1 0 PCM0 Reserved Reserved (R/W) (0) (R/W) (0) (R/W) (0)
Read/write Default value
PPLL0 to PPLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H (R/W) (R/W) (R/W) 000034H (X) (X) (X) 000036H 000038H PPLH0 to PPLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H (R/W) (R/W) (R/W) 000035H (X) (X) (X) 000037H 000039H
4 D04 (R/W) (X)
3 D03 (R/W) (X)
2 D02 (R/W) (X)
1 D01 (R/W) (X)
0 D00 (R/W) (X)
Read/write Default value
12 D12 (R/W) (X)
11 D11 (R/W) (X)
10 D10 (R/W) (X)
9 D09 (R/W) (X)
8 D08 (R/W) (X)
Read/write Default value
42
MB90470 Series
(2) Block Diagram * 8-bit PPG ch 0/2/4 Block Diagram
Peripheral clock 16 divider Peripheral clock 8 divider Peripheral clock 4 divider Peripheral clock 2 divider Peripheral clock
PPG 0/2/4 output enable
PPG0/2/4 A/D converter
PPG 0/2/4 output latch
PEN0
PCNT (down counter) Count clock selection L/H selector Time base counter output clock 512 divider
S RQ
IRQ ch 1/3/5 borrow
PUF0
PIE0
L/H selection
PRLL
PRLBH PPGC0 (output mode control)
PRLL L data bus H data bus
43
MB90470 Series
* 8-bit PPG ch 1/3/5 Block Diagram
Peripheral clock 16 divider Peripheral clock 8 divider Peripheral clock 4 divider Peripheral clock 2 divider Peripheral clock
PPG 1/3/5 output enable
PPG1/3/5 UART0
PPG 1/3/5 output latch
PEN1
PCNT (down counter) Count clock selection L/H selector Time base counter output clock 512 divider
S RQ
IRQ
PUF1
PIE1
L/H selection
PRLL
PRLBH PPGC1 (output mode control)
PRLL L data bus H data bus
44
MB90470 Series
6. 8/16-bit Up-down Counter/Timer
This block is an up-down counter/timer configured with six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and related control circuits. (1) Principal functions * 8-bit count registers for counting in the range 0 to 256. (Also operates in 16-bit x 1 mode for counting in the range 0 to 65535.) * Count clock selection provides four count modes. Count mode Time mode Up/down count mode Phase differential count mode (2 x ) Phase differential count mode (8 x ) * In timer mode, there is a choice of two internal count clocks. Count clock (16 MHz operation) Detection edge 125 ns (8 MHz : divided by 2) 0.5 s (2 MHz : divided by 8) Falling edge detection Rising edge detection Falling/rising edge, both edges' detection Edge detection disabled * In phase differential count mode, to provide counts for encoders for motors, etc., the A phase, B phase, and Z phase of the encoder can be input separately for highly precise counts of rotation angle, rotary speed, etc. * The ZIN pin provides a choice of two functions. ZIN pin Counter clear function Gate function * Compare and reload functions are provided, each available independently or in combination. Both can be started together to provide any desired type of up/down count. Compare/reload function Compare function (outputs interrupt at compare events) Compare function (outputs interrupt and clears count at compare events) Reload function (outputs interrupt and reloads at underflow events) Compare/reload function (outputs interrupt and clears count at compare events, outputs interrupt and reloads at underflow events) Compare/reload disabled * Individually controllable interrupts at compare, reload (underflow) and overflow events. * Count direction flag enables detection of immediately preceding count direction. * Interrupt generation at change of count direction.
* In up/down count mode, there is a choice of external pin input signal detection edge.
45
MB90470 Series
(2) Register List
15 UDCR1 RCR1 Reserved CCRH0 Reserved CCRH1 8 bit 87 UDCR0 RCR0 CSR0 CCRL0 CSR1 CCRL1 8 bit 0
CCRH0 (Counter control register high ch.0)
15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W
Address : 00006DH
M16E R/W
Default value 00000000B
CCRH1 (Counter control register high ch.1)
15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W
Address : 000071H
Default value -0000000B
CCRL0/1 (Counter control register low ch.0/1) Address : 00006CH Address : 000070H
7 UDMS R/W 6 CTUT W 5 UCRE R/W 4 RLDE R/W 3 UDCC W 2 CGSC R/W 1 CGE1 R/W 0 CGE0 R/W
Default value 0X00X000B
CSR0/1 (Counter status register ch. 0/1) Address : 000072H Address : 000074H
7 CSTR R/W 6 CITE R/W 5 UDIE R/W 4 CMPF R/W 3 OVFF R/W 2 UDFF R/W 1 UDF1 R 0 UDF0 R
Default value 00000000B
UDCR0/1 (Up down count register ch. 0/1)
15 14 D16 R 6 D06 R 13 D15 R 5 D05 R 12 D14 R 4 D04 R 11 D13 R 3 D03 R 10 D12 R 2 D02 R 9 D11 R 1 D01 R 8 D10 R 0 D00 R
Address : 000069H
D17 R 7
Default value 00000000B
Address : 000068H
D07 R
Default value 00000000B
RCR0/1 (Reload/compare register ch. 0/1)
15 14 D16 W 6 D06 W 13 D15 W 5 D05 W 12 D14 W 4 D04 W 11 D13 W 3 D03 W 10 D12 W 2 D02 W 9 D11 W 1 D01 W 8 D10 W 0 D00 W
Address : 00006BH
D17 W 7
Default value 00000000B
Address : 00006AH
D07 W
Default value 00000000B
46
MB90470 Series
(3) Block Diagram
Data bus 8 bit CGE1 CGE0 CGSC ZIN0 RCR0 (Reload/compare register 0) CTUT Reload control
Edge/level detection
UCRE
RLDE
UDCC
Counter clear 8 bit UCDR0 (Up/down count register 0)
CES1 CES0 CMS1 CMS0 UDMS AIN0 BIN0 Up-down count clock selection Count clock UDF1 UDF0 CDCF CFIE Interrupt output CITE
Carry UDFF OVFF UDIE
CMPF
Prescaler
CSTR
CLKS
47
MB90470 Series
7. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA request from external peripherals and passes the requests to the F2MC-16L CPU to activate the extended DMA or interrupt processing. (1) Register Descriptions Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register) ENIR Address : 00000CH
7 EN7 R/W 6 EN6 R/W 5 EN5 R/W 4 EN4 R/W 3 EN3 R/W 2 EN2 R/W 1 EN1 R/W 0 EN0 R/W
Default value 00000000B
Interrupt/DTP source register (EIRR : External Interrupt Request Register) EIRR Address : 00000DH
15 ER7 R/W 14 ER6 R/W 13 ER5 R/W 12 ER4 R/W 11 ER3 R/W 10 ER2 R/W 9 ER1 R/W 8 ER0 R/W
Default value 00000000B (note that both registers relate to different interrupts)
Request level setting register (ELVR : External Level Register)
7 6 LA3 R/W 14 LA7 R/W 5 LB2 R/W 13 LB6 R/W 4 LA2 R/W 12 LA6 R/W 3 LB1 R/W 11 LB5 R/W 2 LA1 R/W 10 LA5 R/W 1 LB0 R/W 9 LB4 R/W 0 LA0 R/W 8 LA4 R/W
Address : 00000EH
LB3 R/W 15
Default value 00000000B
Address : 00000FH
LB7 R/W
Default value 00000000B
(2) Block Diagram
F2MC-16 bus 4 Interrupt/DTP enable register 4
4
Gate
Source F/F
Edge detection circuit
Request input
4
Interrupt/DTP source register
8
Interrupt level setting register
48
MB90470 Series
8. 16-bit Input Output Timer
The 16-bit input/output timer is composed of one 16-bit free-run timer module, 6 output compare modules, and 2 input capture modules. These functions can be used to produce output of six independent wave forms based on the 16-bit free-run timer, with input pulse width measurement and external clock period measurement. * List of Registers for All Modules * 16-bit free-run timer
15 0 CPCLR Compare clear register
000066/67H
000062/63H
TCDT
Timer data register
000064/65H
TCCS
Control status register
* 16-bit output compare
15 0 OCCP0 to OCCP5 Compare register
00004A, 4C, 4E, 50, 52, 54H 00004B, 4D, 4F, 51, 53, 55H 000056, 58, 5AH 000057, 59, 5BH
OCS1/3/5
OCS0/2/4
Control status register
* 16-bit input capture
15 0 IPCP0, ICCP1 Compare register
00005C, 5EH 00005D, 5FH 000060H
ICS
Control status register
49
MB90470 Series
* Overall Block Diagram
Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 To blocks
Compare register 0
TQ
OUT0
Compare register 1
TQ
OUT1
Bus
Compare register 2
TQ
OUT2
Compare register 3
TQ
OUT3
Compare register 4
TQ
OUT4
Compare register 5
TQ
OUT5
Input capture 0 Capture register 0 Input capture 1 Capture register 1 Edge selection IN1 Edge selection IN0
50
MB90470 Series
(1) 16-bit Free-run Timer The 16-bit free-run timer is composed of a 16-bit up-down counter and control register. The count value from this timer is used as the base timer for the input capture and output compare modules. * A selection of 8 clock types for counter operation is available. * Counter overflow interrupts can be generated. * By a mode setting, the counter can be initialized when the timer value matches the compare register value for the output compare module. * Register list Compare clear register (CPCLR)
15 14 CL14 (R/W) 13 CL13 (R/W) 12 CL12 (R/W) 11 CL11 (R/W) 10 CL10 (R/W) 9 CL09 (R/W) 8 CL08 (R/W)
000067H
CL15 (R/W)
Default value XXXXXXXXB
7
6 CL06 (R/W)
5 CL05 (R/W)
4 CL04 (R/W)
3 CL03 (R/W)
2 CL02 (R/W)
1 CL01 (R/W)
0 CL00 (R/W)
000066H
CL07 (R/W)
Default value XXXXXXXXB
Timer counter data register (TCDT)
15 14 T14 (R/W) 13 T13 (R/W) 12 T12 (R/W) 11 T11 (R/W) 10 T10 (R/W) 9 T09 (R/W) 8 T08 (R/W)
000063H
T15 (R/W)
Default value 00000000B
7
6 T06 (R/W)
5 T05 (R/W)
4 T04 (R/W)
3 T03 (R/W)
2 T02 (R/W)
1 T01 (R/W)
0 T00 (R/W)
000062H
T07 (R/W)
Default value 00000000B
Timer counter control/status register (TCCS)
15 14 (R/W) 13 (R/W) 12 MSI2 (R/W) 11 MSI1 (R/W) 10 MSI0 (R/W) 9 ICLR (R/W) 8 ICRE (R/W)
000065H
ECKE (R/W)
Default value 0--00000B
7
6 IVFE (R/W)
5 STOP (R/W)
4 MODE (R/W)
3 SCLR (R/W)
2 CLK2 (R/W)
1 CLK1 (R/W)
0 CLK0 (R/W)
000064H
IVF (R/W)
Default value 00000000B
51
MB90470 Series
* Block Diagram
Interrupt request Frequency divider
IVF
IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Clock
Bus
16-bit free-run timer 16-bit compare clear register Count value output T15 to T00
Compare circuit
MSI3 to 0
ICLR
ICRE Interrupt request A/D converter startup
52
MB90470 Series
(2) Output Compare The output compare module consists of a 16-bit compare register, compare output pin unit, and control register. When the value in the compare register in this module matches the value of the 16-bit free-run timer, the pin output level can be inverted and an interrupt generated. * There are six compare registers that can operate independently. Module settings can be used to use the two compare registers to control the output. * The interrupt can be set by a compare match. * Register List Compare register (OCCP0 to OCCP5)
15 14 C14 (R/W) 13 C13 (R/W) 12 C12 (R/W) 11 C11 (R/W) 10 C10 (R/W) 9 C09 (R/W) 8 C08 (R/W)
00004BH 00004DH 00004FH 000051H 000053H 000055H
C15 (R/W)
Default value XXXXXXXXB
6
5 C06 (R/W)
4 C05 (R/W)
3 C04 (R/W)
2 C03 (R/W)
1 C02 (R/W)
0 C01 (R/W) C00 (R/W)
00004AH 00004CH 00004EH 000050H 000052H 000054H
C07 (R/W)
Default value XXXXXXXXB
Control register (OCS1/3/5)
15 14 () 13 () 12 CMOD (R/W) 11 OTE1 (R/W) 10 OTE0 (R/W) 9 OTD1 (R/W) 8 OTD0 (R/W)
000057H 000059H 00005BH
()
Default value ---00000B
Control register (OCS0/2/4)
7 6 ICP0 (R/W) 5 ICE1 (R/W) 4 ICE0 (R/W) 3 () 2 () 1 CST1 (R/W) 0 CST0 (R/W)
000056H 000058H 00005AH
ICP1 (R/W)
Default value 0000--00B
53
MB90470 Series
* Block Diagram
16-bit timer counter value (T15 to T00)
Compare control
TQ
OTE0
OUT0 (2) (4)
Compare register 0 (2) 16-bit timer counter value (T15 to T00) Bus CMOD
Compare control TQ Compare register 1 (3) ICP1 Control unit Control blocks ICP0 ICE0 ICE0 Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt OTE1 OUT1 (3) (5)
54
MB90470 Series
(3) Input Capture The input capture module detects the rising edge, falling edge, or both edges of an input signal and saves the value of the 1-bit free-run timer at that moment in a register. This module can also generate an interrupt when an edge is detected. The input capture module is composed of input capture registers and a control register. Each of the input captures has a corresponding external input pin. * Selection of three valid edges for external input : Rising edge/falling edge/both edges * An interrupt can be generated when the valid edge is detected. * Register List Input capture data registers (IPCP0, IPCP1)
15 14 CP14 (R) 13 CP13 (R) 12 CP12 (R) 11 CP11 (R) 10 CP10 (R) 9 CP09 (R) 8 CP08 (R)
00005DH 00005FH
CP15 (R)
Default value XXXXXXXXB
7
6 CP06 (R)
5 CP05 (R)
4 CP04 (R)
3 CP03 (R)
2 CP02 (R)
1 CP01 (R)
0 CP00 (R)
00005CH 00005EH
CP07 (R)
Default value XXXXXXXXB
Control status register (ICS0, ICS1)
7 6 ICP0 (R/W) 5 ICE1 (R/W) 4 ICE0 (R/W) 3 EG11 (R/W) 2 EG10 (R/W) 1 EG01 (R/W) 0 EG00 (R/W)
000060H
ICP1 (R/W)
Default value 00000000B
* Block Diagram
Capture data register 0
Edge detection
IN0
Bus
16-bit timer counter value (T15 to T00)
EG11 EG10 EG01 EG00
Capture data register 1
Edge detection
IN1
ICP1
ICP0
ICE1
ICE0 Interrupt Interrupt
55
MB90470 Series
9. I2C Interface
The I2C interface is a serial I/O port supporting Inter IC bus operation, and operates as a master/slave device on the I2C bus. The following features are provided. * Master/slave sending and receiving * Arbitration functions * Clock synchronization functions * Slave address/general call address detection functions * Transfer direction detection function * Start condition repeat generator and detection function * Bus error detection function (1) Register List IBSR (bus status register)
7 6 RSC (R) (0) 5 AL (R) (0) 4 LRB (R) (0) 3 TRX (R) (0) 2 AAS (R) (0) 1 GCA (R) (0) 0 FBT (R) (0)
Bit no.
Address : 000088H Read/write Default value IBCR (bus control register)
BB (R) (0)
15
14 BEIE (R/W) (0)
13 SCC (R/W) (0)
12 MSS (R/W) ( 0)
11 ACK (R/W) (0)
10 GCAA (R/W) (0)
9 INTE (R/W) (0)
8 INT (R/W) (0)
Bit no.
Address : 000089H Read/write Default value ICCR (clock control register)
BER (R/W) (0)
7
6 () ()
5 EN (R/W) (0)
4 CS4 (R/W) (X)
3 CS3 (R/W) (X)
2 CS2 (R/W) (X)
1 CS1 (R/W) (X)
0 CS0 (R/W) (X)
Bit no.
Address : 00008AH Read/write Default value IADR (address register)
() ()
15
14 A6 (R/W) (X)
13 A5 (R/W) (X)
12 A4 (R/W) (X)
11 A3 (R/W) (X)
10 A2 (R/W) (X)
9 A1 (R/W) (X)
8 A0 (R/W) (X)
Bit no.
Address : 00008BH Read/write Default value IDAR (data register)
() ()
7
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
Bit no.
Address : 00008CH Read/write Default value
D7 (R/W) (X)
56
MB90470 Series
(2) Block Diagram
ICCR EN F2MC-16 bus I2C enable 5 Clock divider 1 6 7 8 Clock select 1 Peripheral clock
ICCR CS4 CS3 CS2 CS1 CS0
Clock divider 2 2 4 8 16 32 64 128 Clock select 2
256
Sync
Shift clock generator
IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE Interrupt request INTE INT IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable End Bus busy Repeat start Last Bit Send/receive
Shift clock edge change timing
Start/stop condition detector Error First Byte Arbitration lost detector SCL
IRQ
SDA
Start/stop condition generator
IDAR IBSR AAS GCA Slave Global call Slave address compare
IADR
57
MB90470 Series
10. 16-bit reload timer
The 16-bit reload timer provides a choice of two functions, one is an internal clock countdown synchronized with any of 3 types of internal clock, and the other is an event count mode that counts down at detection of a given edge of a pulse input externally. This timer defines an underflow as a transition of the count value from 0000H to FFFFH. Therefore, an underflow will occur at the count value "reload register setting count + 1". The count operation includes a choice of reload mode in which the count set value is reloaded at each underflow event, and one-shot mode in which the count stops at an underflow event. An interrupt can be generated when the counter reaches an underflow, and the timer is DTC compatible. (1) Register List * TMCSR (Timer control status registers) Timer control status register (high)
15 14 () () 13 () () 12 () () 11 CSL1 (R/W) (0) 10 CSL0 (R/W) (0) 9 MOD2 (R/W) (0) 8 MOD1 (R/W) (0)
0000CBH
() ()
Read/write Default value
Timer control status register (low)
7 6 OUTE (R/W) (0) 5 OUTL (R/W) (0) 4 RELD (R/W) (0) 3 INTE (R/W) (0) 2 UF (R/W) (0) 1 CNTE (R/W) (0) 0 TRG (R/W) (0)
0000CAH
MOD0 (R/W) (0)
Read/write Default value
* 16-bit timer register/16-bit reload register TMR/TMRLR (high)
15 14 D14 (R/W) (X) 13 D13 (R/W) (X) 12 D12 (R/W) (X) 11 D11 (R/W) (X) 10 D10 (R/W) (X) 9 D09 (R/W) (X) 8 D08 (R/W) (X)
0000CDH
D15 (R/W) (X)
Read/write Default value
TMR/TMRLR (low)
7 6 D06 (R/W) (X) 5 D05 (R/W) (X) 4 D04 (R/W) (X) 3 D03 (R/W) (X) 2 D02 (R/W) (X) 1 D01 (R/W) (X) 0 D00 (R/W) (X)
0000CCH
D07 (R/W) (X)
Read/write Default value
58
MB90470 Series
(2) Block Diagram
Internal data bus
TMRLR 16-bit reload register Reload signal TMR 16-bit timer register (down counter) CLK Count clock generator circuit Gate input UF Reload control circuit
Machine clock
Prescaler Clear
3
Valid clock decision circuit CLK
Wait signal
Output signal generator circuit Pin (TIN0) Input control circuit External clock OUTL Function select 3 Select signal 2 RELD Invert Output signal generator circuit EN
To A/D converter
Clock selector
Pin (TOT0)
Operation control circuit OUTE
Timer control status register (TMCSR)
59
MB90470 Series
11. PG Timer
The PG timer produces a pulse output according to an external input signal. (1) Register List PGCSR (PG control/status register) Operating mode control register
7 6 PE1 (R/W) (0) 5 PE0 (R/W) (0) 4 PMT1 (R/W) (0) 3 PMT0 (R/W) (0) 2 () () 1 () () 0 () ()
00008EH
PEN0 (R/W) (0)
Read/write Default value
(2) Block Diagram
MT00
MT01
Output enable MT00 output latch MT00 output latch
Control circuit
EXTC
60
MB90470 Series
12. PWC (Pulse Width Count) Timer
The PWC timer is a 16-bit multi-function up-count timer with an input signal pulse width measurement function. The hardware includes a total of three channels, each with one 16-bit up-count timer, one input pulse divider and divider ration control register, one measurement input pin, and one 16-bit control register. The following functions are provided : Timer functions : An interrupt can be generated each time a set time interval elapses. A choice of three internal reference clocks is available. Pulse width measurement functions : Measures the time between designated events on an externally input pulse signal. The reference clock is selected from three internal clock signals. Measurement modes : 1) H pulse width ( to ) /L pulse width ( to ) 2) Rise period ( to ) /fall period ( to ) 3) Measurement between edges (high or low to low or high) An 8-bit input divider can divide the input pulse into 22n divisions (n = 1, 2, 3, 4) and measure the divisions. An interrupt can be generated when measurement is ended. Both one-time and continuous measurement are enabled.
61
MB90470 Series
(1) Register List
15 87 PWCSR0 to PWCSR2 PWC0 to PWC2 DIVR0 to DIVR2 0 (R/W) (R/W) (R/W)
PWCSR0 to PWCSR2 (PWC control/status registers) 000077H 00007BH 00007FH
15 STRT (R/W) (0) 7 CKS1 (R/W) (0) 14 STOP (R/W) (0) 6 CKS0 (R/W) (0) 13 EDIR (R) (0) 5 PIS1 (R/W) (0) 12 EDIE (R/W) (0) 4 PIS0 (R/W) (0) 11 OVIR (R/W) (0) 3 S/C (R/W) (0) 10 OVIE (R/W) (0) 2 MOD2 (R/W) (0) 9 ERR (R) (0) 1 MOD1 (R/W) (0) 8
Reserved
() (X) 0 MOD0 (R/W) (0)
Read/write Default value
000076H 00007AH 00007EH
Read/write Default value
PWCR0 to PWCR2 (PWC data buffer registers) 000079H 00007DH 000081H
15 D15 (R/W) (0) 7 D7 (R/W) (0) 14 D14 (R/W) (0) 6 D6 (R/W) (0) 13 D13 (R/W) (0) 5 D5 (R/W) (0) 12 D12 (R/W) (0) 4 D4 (R/W) (0) 11 D11 (R/W) (0) 3 D3 (R/W) (0) 10 D10 (R/W) (0) 2 D2 (R/W) (0) 9 D9 (R/W) (0) 1 D1 (R/W) (0) 8 D8 (R/W) (0) 0 D0 (R/W) (0)
Read/write Default value
000078H 00007CH 000080H
Read/write Default value
DIVR0 to DIVR2 (Divider control register) 000082H 000084H 000086H
7 () (X) 6 () (X) 5 () (X) 4 () (X) 3 () (X) 2 () (X) 1 DIV1 (R/W) (0) 0 DIV0 (R/W) (0)
Read/write Default value
62
MB90470 Series
(2) Block Diagram
PWCR read Error detector ERR
PWCR 16 Reload Data transfer Overflow 16-bit up/down timer F2MC-16 bus Timer clear Control circuit Start edge End edge selection selection Measure start edge Edge detection Measure end edge Measurement end interrupt request PIS0/PIS1 16 Clock 22 Clock divider 23 CKS1/CKS0 Count enable Internal clock (machine clock / 4)
Divider clear
Control bit output
Flag set etc.
Divider on/off
Input waveform comparator
PWC0 PWC1
8-bit divider
Overflow interrupt request 15
ERR
CKS0/CKS1 Divider select
PWCSR 2
DIVR
63
MB90470 Series
13. Watch Timer
The watch timer is a 15-bit timer using a sub-clock signal. This timer can generate interval interrupts. Also, by a register setting, it can be used as a clock source for the watchdog timer. (1) Register List Watch timer control register (WTC)
7 6 SCE (R) (0) 5 WTIE (R/W) (0) 4 WTOF (R/W) (0) 3 WTR (R/W) (1) 2 WTC2 (R/W) (0) 1 WTC1 (R/W) (0) 0 WTC0 (R/W) (0)
0000AAH
WDCS (R/W) (1)
Default value
(2) Block Diagram
Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear 28 Sub-clock Watch counter 29 210 211 212 213 210 213 214 215 214 Interval selector Interrupt generator circuit Watch timer interrupt
To watchdog timer
64
MB90470 Series
14. Watchdog Timer
The watchdog timer is a 2-bit counter that uses a count clock signal output by the timer base timer or watch timer and will reset the CPU unless cleared within a specified period of time. (1) Register List Watchdog timer control register (WDTC)
7 6 5 4 ERST (R) (X) 3 SRST (R) (X) 2 WTE (W) (1) 1 WT1 (W) (1) 0 WT0 (W) (1)
0000A8H
PONR Reserved WRST (R) (X) () (X) (R) (X)
Default value
(2) Block Diagram
Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 Watch timer control register (WT0) WDCS bit 2 Watch mode start Time base timer mode start Sleep mode start Hold status start Clock select register (CKSCR) SCM bit
Watchdog timer Count clock selector CLR
CLR and start
CLR Internal reset generator circuit
Counter clear control circuit Stop mode start
2-bit counter
Watchdog reset generator circuit
4 Clear Time base counter HCLK signal / 2 x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 4
SCLK
x 21 x 2 2
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
HCLK : Oscillator clock SCLK : Sub-clock
65
MB90470 Series
15. Time Base Timer
The time base timer is an 18-bit free-run timer that counts up in synchronization with the internal count clock (base oscillator divided by 2) . It functions as an interval timer with a selection of four types of time intervals. Other functions of this timer also include output of a timer signal for the oscillator stabilization wait time and an operating clock signal for the watchdog timer. (1) Register List Time base timer control register (TBTC)
15 14 () (X) 13 () (X) 12 TBIE (R/W) (0) 11 TBOF (R/W) (0) 10 TBR (W) (1) 9 TBC1 (R/W) (0) 8 TBC0 (R/W) (0)
0000A9H
RESV (R/W) (1)
(2) Block Diagram
To PPG timer Time base timer/ counter HCLK signal /2 x 21 x 2 2 To watchdog timer
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF
Power-on reset Stop mode start Mode start Hold status start CKSCR : MCR = 1 0*1 CKSCR : SCS = 0 1*2
Counter clear control circuit Interval timer selector TBOF set TBOF clear
Clock control unit Oscillator stabilization wait To interval selector
Time base timer control register (TBTC)
RESV
TBIE TBOF TBR TBC1 TBC0
Time base timer interrupt signal
OF HCLK *1 *2
: Not used : Overflow : Oscillator clock : Switches machine clock from main clock or sub-clock to PLL clock. : Switches machine clock from sub-clock to main clock.
66
MB90470 Series
16. Clock
The clock generator module controls the operation of the internal clocks that produce the operating clock signals for the CPU and peripheral devices. This internal clock signal is called the machine clock, and one period is called a machine cycle. The clock signal from the base oscillator is called the oscillator clock, and the clock signal generated by the internal PLL module is called the PLL clock. (1) Register List Clock select register (CKSCR)
15 14 MCM (R) (1) 13 WS1 (R/W) (1) 12 WS0 (R/W) (1) 11 SCS (R/W) (1) 10 MCS (R/W) (1) 9 CS1 (R/W) (0) 8 CS0 ( R/W ) (0)
0000A1H
SCM (R) (1)
Default value
67
MB90470 Series
(2) Block Diagram
Standby control circuit Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0
Reserved
Pin High-Z control circuit RST pin CPU intermittent operation selector Internal reset generator circuit
Pin high-impedance control Internal reset
Intermittent cycle selection CPU clock control circuit CPU clock
Interrupt release
Standby control circuit
Stop, sleep signals Stop signal Peripheral clock control circuit Oscillator stabilization wait release Peripheral clock
Machine clock Clock generator module Clock selector Divide by 4 SCLK 2
2
Oscillator stabilization wait period selector
PLL multiplier circuit Sub-clock generator circuit X0A X1A pin pin X0 X1 pin pin System clock generator circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR)
Divide by 2
Divide by 1024
Divide by 2
Divide by 4
Divide by 4
Divide by 4
Divide by 2
HCLK
MCLK Time base timer
To watchdog timer
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub-clock
68
MB90470 Series
(3) Clock Signal Supply Map
Clock generator ratio Watch timer X0A pin X1A pin 4 Peripheral function Watchdog timer 4 8/16-bit PPG timer 0 Sub-clock generator circuit Time base timer 8/16-bit PPG timer 1 1 2 3 4 8/16-bit PPG timer 2 PLL multiplier circuit
Divide by 4
PPG0, PPG1 pin PPG2, PPG3 pin PPG4, PPG5 pin
X0 pin X1 pin System clock generator circuit
Divide by 2
SCLK
PCLK 16-bit reload timer
TIN0 pin TOT0 pin
Clock selector
HCLK
MCLK SCK0, SIN0 pin
CPU, DMA
UART
SOT0 pin SCK1, SCK2, SIN1, SIN2 pin SOT1, SOT2 pin
I/O expansion serial interface 2 ch
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16-bit U/D counter pin
Chip select
CS0, CS1, CS2, CS3 pin OUT0, OUT1,OUT2, OUT3, OUT4, OUT5 pin FRCK pin IN0, IN1 pin AN0 to AN7, ADTG pin IRQ0 to IRQ7 pin IN0, IN1 pin
16-bit output compare
16-bit free-run timer
16-bit input capture
10-bit A/D converter
External interrupt
PG
MT00, MT01 pin SCL, SDA pin PWC1, PWC2, PWC3 pin
HCLK MCLK SCLK PCLK
: Oscillator clock : Main clock : Sub-clock : PLL clock : Machine clock
3
I2C interface
16-bit PWC 3ch
Oscillator stabilization wait control
69
MB90470 Series
17. Low Power Modes
The MB90470 series uses a selection of operating clock signals and clock operation controls to provide the following CPU operating modes. * Clock modes (PLL clock mode, main clock mode, sub-clock mode) * CPU intermittent operation modes (PLL clock intermittent operation mode, main clock intermittent operation mode, sub-clock intermittent operation mode) * Standby mode (Sleep mode, time base timer mode, stop mode, watch mode) (1) Register List Low power mode control register (LPMCR)
7 6 SLP (W) (0) 5 SPL (R/W) (0) 4 RST (W) (1) 3 TMD (R/W) (1) 2 CG1 (R/W) (0) 1 CG0 (R/W) (0) 0
Reserved
0000A0H
STP (W) (0)
(R/W) (0)
Default value
70
MB90470 Series
(2) Block Diagram
Standby control circuit Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0
Reserved
Pin High-Z control circuit RST pin CPU intermittent operation selector Internal reset generator circuit
Pin high-impedance control Internal reset
Intermittent cycle selection CPU clock control circuit CPU clock
Interrupt release
Standby control circuit
Stop, sleep signals Stop signal Peripheral clock control circuit Oscillator stabilization wait release Peripheral clock
Machine clock Clock generator module Clock selector Divide by 4 SCLK 2
2
Oscillator stabilization wait period selector
PLL multiplier circuit Sub-clock generator circuit X0A X1A pin pin X0 X1 pin pin System clock generator circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR)
Divide by 2
Divide 1024
Divide by 2
Divide by 4
Divide by 4
Divide by 4
Divide by 2
HCLK
MCLK Time base timer
To watchdog timer
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub-clock
71
MB90470 Series
(3) Status Transition Chart
External reset, watchdog timer reset, software reset Power on Reset Power-on reset Oscillator stabilization wait end MCS = 0 Main clock mode SLP = 1 Interrupt MCS = 1 PLL clock mode SLP = 1 Interrupt SCS = 0 SCS = 1 SCS = 0 SCS = 1 Sub-clock mode SLP = 1 Interrupt
Main sleep mode TMD = 0 Interrupt
PLL sleep mode TMD = 0 Interrupt
Sub-sleep mode TMD = 0 Interrupt
Time base timer mode STP = 1 Main stop mode Interrupt Oscillator stabilization wait end STP = 1
Time base timer mode
Watch mode STP = 1 Sub-stop mode Interrupt Oscillator stabilization wait end
PLL stop mode Interrupt Oscillator stabilization wait end
Main clock oscillator stabilization wait
Main clock oscillator stabilization wait
Sub-clock oscillator stabilization wait
72
MB90470 Series
18. Overview of the Chip Select Function
This module issues chip select signals in order to facilitate connection to external memory. There are four chip select output pins, with hardware areas set using a register for each output, so that the select signal is output from the related pin whenever access to an external address is detected. * Features of the chip select function The chip select function has two 8-bit registers for settings for each of the four output pins. One register (CARx) is used to specify the upper 8 bits of the address for match detection, thereby providing memory area detection in 64 KB units. The other register (CMRx) can be set to detect areas larger than 64 KB by masking bits in the match detection value. Note that the CS output is set to high impedance during a bus hold condition. (1) Register List
15 CAR0 CAR1 CAR2 CAR3 CALR 87 CMR0 CMR1 CMR2 CMR3 CSCR 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Chip select area MASK register (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H
7 M7 (R/W) (0) 6 M6 (R/W) (0) 5 M5 (R/W) (0) 4 M4 (R/W) (0) 3 M3 (R/W) (1) 2 M2 (R/W) (1) 1 M1 (R/W) ( 1) 0 M0 (R/W) (1)
Read/write Default value
Chip select area register (CARx) 0000C1H 0000C3H 0000C5H 0000C7H
15 A7 (R/W) (1) 14 A6 (R/W) (1) 13 A5 (R/W) (1) 12 A4 (R/W) (1) 11 A3 (R/W) (1) 10 A2 (R/W) (1) 9 A1 (R/W) (1) 8 A0 (R/W) (1)
Read/write Default value
Chip select control register (CSCR)
7 6 () () 5 () () 4 () () 3 OPL3 (R/W) (0) 2 OPL2 (R/W) (0) 1 OPL1 (R/W) (0) 0 OPL0 (R/W) ()
0000C8H
() ()
Read/write Default value
Chip selector active level register (CALR)
15 14 () () 13 () () 12 () () 11 ACTL3 (R/W) (0) 10 ACTL2 (R/W) (0) 9 ACTL1 (R/W) (0) 8 ACTL0 (R/W) (0)
0000C9H
() ()
Default value
73
MB90470 Series
(2) Block Diagram
FMC-16 bus
CMRx
CARx Chip select output pin A23 to A16
74
MB90470 Series
19. ROM Mirror Function Select Module
The ROM mirror function select module provides a register selection that allows the FF bank in ROM to be viewed in the 00 bank. (1) Register List bit ROMM Address : 00006FH
15 14 13 12 11 10 9 8 MI W
Default value - - - - - - - 1B
W : Write only - : Not used
(2) Block Diagram
F2MC-16LX ROM mirror function select
Address area
FF bank
00 bank
ROM
Note : Do not access this register during operations to address 004000H to 00FFFFH.
75
MB90470 Series
20. Interrupt Controller
The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for each I/O with an interrupt function. The registers have the following functions. * Set the interrupt level of the corresponding peripheral. (1) Register List Interrupt control register Address: ICR01: 0000B1H
ICR03: 0000B3H bit ICR05: 0000B5H ICR07: 0000B7H 15 ICR09: 0000B9H ICR11: 0000BBH ICR13: 0000BDH ICR15: 0000BFH Read/Write (W) Initial value (0)
14 (W) (0)
13 (W) (0)
12 (W) (0)
11 Reserved (R/W) (0)
10 IL2
9 IL1
8 IL0 (R/W) (1)
ICR01, 03, 05, 07, 09, 11, 13, 15
(R/W) (R/W) (1) (1)
Address: ICR00: 0000B0H bit ICR02: 0000B2H
ICR04: 0000B4H ICR06: 0000B6H ICR08: 0000B8H ICR14: 0000BEH 15 14 (W) (0) 13 (W) (0) 12 (W) (0) 11 Reserved (R/W) (0) 10 IL2 9 IL1 8 IL0 (R/W) (1)
ICR00, 02, 04, 26, 08, 10, 12, 14
Read/Write (W) Initial value (0)
(R/W) (R/W) (1) (1)
Note : Do not access these registers using read-modify-write instructions as this can cause misoperation. (2) Block Diagram
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Re se r ve d
3 I L2 I L1 IL0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
32
Interrupt request (peripheral resource)
F2MC-16LX Bus
Determine priority of interrupt
3
(CPU) Interrupt level
76
MB90470 Series
21. DMA
DMA is the simplified DMA which has the equivalent function to EI2OS function DMA has DMA transfer channel which consists of 16 channels and has the following functions. * Automatic data transfer between peripheral resources (I/O) and memory. * CPU program executing stops dring DMA operation. * Selectable for address transfer increase/decrease . * DMA transfer control is done at DMA enable register, DMA stop status register, DMA status register and descriptor. * Stop request stops DMA transfer from resources. * After DMA transfer, flag is set to bit corresponding to DMA status register transfer stop channel and stop interrupt is output to interrupt controller. (1) Register List DMA enable register
bit DERH : 0000ADH
15 EN15 (R/W) 14 EN14 (R/W) 13 EN13 (R/W) 12 EN12 (R/W) 11 EN11 (R/W) 10 EN10 (R/W) 9 EN9 (R/W) 8 EN8 (R/W)
Initial value
0 0 0 0 0 0 0 0B
DMA enable register
bit DERL : 0000ACH
7 EN7 (R/W) 6 EN6 (R/W) 5 EN5 (R/W) 4 EN4 (R/W) 3 EN3 (R/W) 2 EN2 (R/W) 1 EN1 (R/W) 0 EN0 (R/W)
Initial value
0 0 0 0 0 0 0 0B
DMA stop status register
bit DSSR : 0000A4H
7 STP7 (R/W) 6 STP6 (R/W) 5 STP5 (R/W) 4 STP4 (R/W) 3 STP3 (R/W) 2 STP2 (R/W) 1 STP1 (R/W) 0 STP0 (R/W)
Initial value
0 0 0 0 0 0 0 0B
DMA status register
bit DSRH : 00009DH
15 DE15 (R/W) 14 DE14 (R/W) 13 DE13 (R/W) 12 DE12 (R/W) 11 DE11 (R/W) 10 DE10 (R/W) 9 DE9 (R/W) 8 DE8 (R/W)
Initial value
0 0 0 0 0 0 0 0B
DMA status register
bit DSRL : 00009CH
7 DE7 ( R/W ) 6 DE6 ( R/W ) 5 DE5 ( R/W ) 4 DE4 ( R/W ) 3 DE3 (R/W) 2 DE2 (R/W) 1 DE1 (R/W) 0 DE0 (R/W)
Initial value
0 0 0 0 0 0 0 0B
77
MB90470 Series
(2) Block Diagram Memory area
by IOA
I/O register
I/O register
Peripheral functions (I/O) DMA transfer request F2MC-16LX Bus
Not transfer stop DMA descriptor
by BAP
DER read
DMA controller At transfer stop
Buffer Transfer
by DCT
CPU
Interrupt controller
IOA : Address pointer BAP : Buffer address pointer DER : DMA enable register (ENx selection is done.) DTC : Data counter
78
MB90470 Series
22. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List * Auto ready function select register (ARSR) Address : 0000A5H
bit 15 ICR1 W bit 14 ICR0 W bit 13 HMR1 W bit 12 HMR0 W bit 11 bit 10 bit 9 LMR1 W bit 8 LMR0 W
Initial value 0011- - 00B
* External address output control register (HACR) Address : 0000A6H
bit 7 E23 W bit 6 E22 W bit 5 E21 W bit 4 E20 W bit 3 E19 W bit 2 E18 W bit 1 E17 W bit 0 E16 W
Initial value 00000000B
* Bus control signal select register (EPCR) Address : 0000A7H
bit 15 CKE W bit 14 RYE W bit 13 HDE W bit 12 ICBS W bit 11 HMBS W bit 10 WRE W bit 9 LMBS W bit 8
Initial value 100010 -B
W - *
: Write only : Not used : May be either "1" or "0"
(2) Block Diagram
P5 P2 P3 P4 P5
P0
P1
P0 data P0 direction
P0
RB
Data control
Address control
Access control
Access control
79
MB90470 Series
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration * Program address detection register 0 to 2 (PADR0)
Address PADR0 (Low order address): 001FF0H R/W Address PADR0 (Middle order address): 001FF1H R/W Address PADR0 (High order address): 001FF2H R/W Address PADR1 (Low order address): 001FF3H R/W Address PADR1 (Middle order address): 001FF4H R/W Address PADR1 (High order address): 001FF5H R/W Address 00009EH bit 7 RESV R/W R/W :Readable and writable X :Undefined RESV:Reserved bit R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 AD0E R/W R/W bit 0 RESV R/W Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B
* Program address detection register 3 to 5 (PADR1)
* Program address detection control status register (PACSR)
RESV RESV R/W R/W RESV AD1E RESV R/W R/W R/W
80
MB90470 Series
(2) Block Diagram
Internal data bus
Address detection register
Compare
Address latch
INT9 instruction
Enable bit
F2MC-16LX CPU core
81
MB90470 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 - 40 - 55 Max VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 + 2.0 20 10 3 60 30 - 10 -3 - 60 -30 410 + 85 + 150 (VSS = AVSS = 0.0 V) Symbol VCC3 Supply voltage VCC5 AVCC AVRH Input voltage Output voltage Maximum clamp current Total maximum clump current "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature VI VO ICLAMP | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *2 *2 *2 *2 *6 *6 *3 *4 *1 Remarks
Parameter
*1: AVCC and AVRH must not exceed VCC3. Also, AVRH must not exceed AVCC ,too. *2: VI, and VO must not exceed VCC (including VCC3, VCC5) plus 0.3 V. *3: Maximum output current is defined as the peak value at one corresponding pin. *4: Average output current is defined as the average current flowing through one corresponding pin in an interval of 100 ms. *5: Average total output current is defined as the total average current flowing through all corresponding pins in an interval of 100 ms. *6: * Applicable to pins: General purpose CMOS input port (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3) * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. (Continued)
82
MB90470 Series
(Continued)
* The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Sample recommended circuits: * Input/output equivalent circuits
Protective diode
Vcc
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
83
MB90470 Series
2. Recommended Operating Conditions
Value Min 1.8 VCC3* 2.4 3.0 1.8 VCC5* Supply voltage VCC3 2.4 3.0 1.8 1.8 VCC5 1.8 VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage VILS VILM Operating temperature TA 0.7 VCC 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 40 5.5 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 + 85 V V V V V V V C Max 3.6 3.6 3.6 5.5 5.5 5.5 3.6 5.5
(VSS = AVSS = 0.0 V) Unit V V V V V V V V Remarks MASK version Low voltage FLASH version High speed FLASH version MASK version Low voltage FLASH version High speed FLASH version Hold stop status Hold stop status (MASK version) Hold stop status (FLASH version) All pins other than VHIS, VIHM pins Hysteresis input pins MD pin input All pins other than VILS, VILM pins Hysteresis input pins MD pin input
Parameter
Symbol
* : Pay attention to operating frequency. Note : When using I2C functions, the voltage should be at least 2.4 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90470 Series
3. DC Characteristics
(MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * (Low voltage FLASH version : VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * (High speed FLASH version : VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * Conditions VCC = 2.7 V IOH = - 1.6 mA VCC = 4.5 V IOH = - 4.0 mA VCC = 2.7 V IOL = 2.0 mA VCC = 4.5 V IOL = 4.0 mA VCC = 3.3 V VSS < VI < VCC VCC = 3.0 V, at TA = + 25 C Value Min VCC3 - 0.3 VCC5 - 0.5 Typ Max 0.4 Unit V Using 5 V system power supply Remarks
Parameter
Symbol
Pin name
"H" level output voltage
VOH
All pins except P76-P77
V
"L" level output voltage
V Using 5 V system power supply
VOL
All output pins
0.4
V
Input leak current Pull-up resistance Open drain output current
IIL
All pins except P76, P77 P40 to P47, P70 to P77
- 10 20
65
+ 10 200
A k A mA MASK version mA MASK version (A/D operation) FLASH version (A/D operation)
RPULL
Ileak
0.1 60 65 51 56
10 80 85 66 71.5
ICC
at VCC = 3.3 V, at normal internal 20 MHz operation

mA FLASH version mA
Supply current ICCS
at VCC = 3.3 V, flash write/erase at internal 20 MHz VCC = 3.3 V, sleep mode at 20 MHz at VCC = 3.3 V, sub operation, external 32 kHz, internal 8 kHz operation (TA = + 25 C)
57
71.5
mA FLASH version
18
33
mA
ICCL
16
140
A
* : Pay attention to operating frequency.
(Continued)
85
MB90470 Series
(Continued)
(MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * (Low voltage FLASH version : VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * (High speed FLASH version : VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) * Symbol Pin name Conditions at VCC = 3.3 V, watch operation, external 32 kHz, internal 8 kHz operation (TA = + 25 C) TA = + 25 C, stop mode, at VCC = 3.3 V Value Min Typ 10 Max 40 Unit A Remarks MASK version
Parameter
ICCT Supply current ICCH
15
40
A
FLASH version
All pins except AVCC, AVSS, VCC, VSS

0.1 0.2
20 40
A A
MASK version FLASH version
Input capacitance
CIN
5
15
pF
* : Pay attention to operating frequency. Notes : * Pins P40-P47 and P70-P75 are N-ch open drain pins with controls, and normally used at CMOS level. * P76 and P77 are N-ch open drain pins. * VCC = VCC3 = VCC5. * When using two power supplies, the 5 V system pins are P20 to P27, P30 to P37, P40 to P47 and P70 to P77. All other pins are 3 V input/output pins.
86
MB90470 Series
4. AC Characteristics
(1) Clock Timing Ratings Symbol (VSS = 0.0 V, TA = -40 C to +85 C) Pin name Conditions Value Min 3 Clock frequency FCH X0, X1 3 FCL Clock cycle time tC tCL PWH PWL PWLH PWLL tcr tcf fCP Internal operating clock frequency fCPL X0A, X1A X0, X1 X0A, X1A X0 X0A X0 25 5 1.5 1.5 3 3 Internal operating clock cycle time *1 : VCC = VCC3 = VCC5 *2 : Observe the operating voltage with care. tCP tCPL 50.0 62.5 32.768 30.5 15.2 8.192 122.1 40 333 5 20 16 20 12 666 666 kHz ns s ns s ns *1 *1 Using external clock *2 Typ Max 20 MHz Unit Remarks for crystal oscillation*2 for external clock
Parameter
Input clock pulse width
Input clock rise, fall time
MHz *2 MHz MB90474 only kHz MHz MB90F474H MHz MB90F474L ns ns s *2 MB90474 only
87
MB90470 Series
* X0, X1 clock timing
tC
X0
PWH tcf PWL tcr
0.8 VCC 0.2 VCC
* X0A, X1A clock timing
tCL
X0A
PWLH tcf PWLL tcr
0.8 VCC 0.2 VCC
88
MB90470 Series
* PLL warranted operating range Internal operating clock frequency vs. Supply voltage
High speed flash model operating range 3.6 PLL warranted operating range
Supply voltage VCC (V)
3.13 3.0 2.5 2.4 1.8
Low voltage flash model operating range Normal operating range
1.5
3
5
12 10 Internal clock fCP (MHz)
16
20
Note : Use it at f = 16 MHz for MB90474. When using the high speed flash model at f = 20 MHz, use supply voltages of 3.13 V to 3.6 V. For A/D operating frequencies, see the electrical characteristics of the A/D converter module. Maximum assured operation frequency (fcp) of DMA is 16 MHz. Base oscillator frequency vs. Internal operating clock frequency
20
Internal clock fCP (MHz)
16 12 9 8 4
34
8 10
16 20 24 Base oscillator clock FC (MHz)
32
40
Note : Use PLL circuit when using internal clock at 16 MHz or more. It is recommended to use base oscillator clock of up to 20 MHz. AC characteristics are determined using the following measurement reference voltage values. * Input signal waveform Hysteresis input pins
0.8 VCC 0.2 VCC
* Output signal waveform Output pins
2.4 V 0.8 V
Pins other than hysteresis input/MD input pins
0.7 VCC 0.3 VCC
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MB90470 Series
(2) Clock Output Timing SymPin name bol tCYC tCHCL CLK CLK Value Min tCP Max
(VSS = 0.0 V, TA = -40 C to +85 C) Conditions Unit ns ns ns ns at fcp = 20 MHz at fcp = 16 MHz at fcp = 5 MHz Remarks
Parameter Cycle time CLK to CLK
VCC = 3.0 V to 3.6 V tCP / 2 - 15 tCP / 2 + 15 VCC = 2.7 V to 3.3 V tCP / 2 - 20 tCP / 2 + 20 VCC = 2.7 V to 3.3 V tCP / 2 - 64 tCP / 2 + 64 Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
90
MB90470 Series
(3) Reset Input Ratings
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Conditions Value Min 16 tCP Max Unit ns ms Remarks In normal operation In stop mode
Parameter
Symbol
Reset input time
tRSTL
RST
Oscillator oscillation time* + 16 tCP
* : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred s to a few ms, and for an external clock this is 0 ms. Note: tCP : See (1) Clock Timing Ratings. * In stop mode
tRSTL RST
0.2 Vcc
90 % of amplitude
0.2 Vcc
X0
Internal operation clock
Oscillator oscillation time
16 tcp
Oscillator stabilization wait time
Execution of the instruction
Internal reset
* Measurement conditions for AC ratings CL : Load capacitance applied to pin during testing Pin CLK, ALE, CL = 30 pF AD15 to AD00 (Address, data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 80 pF
CL
91
MB90470 Series
(4) Power On Ratings (Power-on reset) Symbol tR tOFF Pin name VCC VCC Conditions
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Min 1 Max 30 Unit ms ms * For continuous operation Remarks
Parameter Power rise time Power cutoff time
* : Power supply rise time requires VCC < 0.2 V. Notes : * VCC = VCC3 = VCC5 * The above ratings are values for power-on reset. * A power-on reset should be applied by restarting the power supply inside the device.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Extreme variations in supply voltage may activate a power-on reset. As the illustration shows below , when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended.
Main supply voltage VCC Sub supply voltage VSS
Hold RAM data A rise slope of 50 mV or less is recommended
92
MB90470 Series
(5) Bus read timing Symbol Conditions
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Value Min tCP / 2 - 15 tCP / 2 - 20 tCP / 2 - 35 tCP / 2 - 20 tCP / 2 - 40 tCP / 2 - 15 tCP - 20 3 tCP / 2 - 25 3 tCP / 2 - 20 0 tCP / 2 - 15 tCP / 2 - 10 tCP / 2 - 20 tCP / 2 - 20 tCP / 2 - 15 Max 5 tCP / 2 - 60 5 tCP / 2 - 80 3 tCP / 2 - 60 3 tCP / 2 - 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns at fcp = 8 MHz at fcp = 8 MHz at fcp = 20 MHz at fcp = 16 MHz at fcp = 8 MHz Remarks at fcp = 20 MHz at fcp = 16 MHz at fcp = 8 MHz
Parameter
ALE pulse width Valid address ALE time ALE address valid time Valid address RD time Valid address valid data input RD pulse width RD valid data input RD data hold time RD ALE time RD address valid time Valid address CLK time RD CLK time ALE RD time
tLHLL
ALE
tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL
Address pins, ALE ALE, Address pins RD, address Address/data RD RD, Data RD, Data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
93
MB90470 Series
tAVCH 2.4 V
tRLCH 2.4 V
CLK
tRHLH
ALE
2.4 V tLHLL
2.4 V 0.8 V tRLRH
2.4 V
RD
2.4 V tAVLL tLLAX tLLRL 0.8 V
Multiplex mode
A23 to A16
2.4 V 0.8 V
tAVRL
tRLDV
tRHAX 2.4 V 0.8 V
tAVDV
tRHDX 0.7 VCC Read data 0.3 VCC tRHAX 0.7 VCC 0.3 VCC
AD15 to AD00
2.4 V Address 0.8 V
2.4 V 0.8 V
Non-multiplex mode
A23 to A00
2.4 V 0.8 V tRLDV tAVDV
2.4 V 0.8 V
tRHDX 0.7 VCC Read data 0.3 VCC 0.3 VCC 0.7 VCC
D15 to D00
94
MB90470 Series
(6) Bus Write Timing Symbol tAVWL tWLWH tDVWH
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Address pins, WR WRL, WRH Data pins, WR WR, Data pins WR, Address pins WR , ALE WR , CLK Conditions Value Min tCP - 20 3 tCP / 2 - 25 3 tCP / 2 - 20 3 tCP / 2 - 20 15 20 30 tCP / 2 - 10 tCP / 2 - 15 tCP / 2 - 20 Max Unit ns ns ns ns ns ns ns ns ns ns at fcp = 20 MHz at fcp = 16 MHz at fcp = 8 MHz at fcp = 20 MHz at fcp = 16 MHz Remarks
Parameter Valid address WR time WR pulse width Valid data output WR time WR data hold time
tWHDX

WR address valid time tWHAX WR ALE time WR CLK time tWHLH tWLCH
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
95
MB90470 Series
tWLCH 2.4 V
CLK
tWHLH
ALE
tWLWH 2.4 V
2.4 V
WR (WRL, WRH)
0.8 V
Multiplex mode
A23 to A16
2.4 V 0.8 V
tAVWL
tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V Write data 0.8 V tWHAX 0.8 V
AD15 to AD00
2.4 V Address 0.8 V
2.4 V
Non-multiplex mode
A23 to A00
2.4 V 0.8 V tDVWH
2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V
D15 to D00
2.4 V 0.8 V
96
MB90470 Series
(7) Ready Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol tRYHS tRYHH Pin name Conditions RDY Value Min 45 70 0 Max Unit ns ns ns fcp = 8 MHz Remarks
Parameter RDY setup time RDY hold time
Notes : * If the RDY setup time is not sufficient, use the auto ready function. * VCC = VCC3 = VCC5 * If input from the RDY pin, note that the AC ratings must be satisfied so that the chip will not drive recklessly.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS tRYHH
RDY wait not applied RDY wait applied (1 cycle)
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC tRYHS
97
MB90470 Series
(8) Hold Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol tXHAL tHAHV Pin name HAK HAK Conditions Value Min 30 tCP Max tCP 2 tCP Unit ns ns Remarks
Parameter Pin floating HAK time HAK valid data time
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5 * If the HRQ pin is read, at least one cycle is required before the HAK pin changes.
HAK
0.8 V tXHAL 2.4 V
2.4 V tHAHV High-Z 2.4 V 0.8 V
All pins
0.8 V
98
MB90470 Series
(9) UART Timing Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name External shift clock mode output pin CL = 80 pF + 1 TTL Internal shift clock mode output pin CL = 80 pF + 1 TTL
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Conditions Value Min 8 tCP - 80 - 120 100 200 tCP 4 tCP 4 tCP 60 120 60 120 Max + 80 + 120 150 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz Remarks
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Notes : * These AC characteristics are for operation in CLK synchronous mode. * CL is the load capacitance applied to pins during testing. * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
99
MB90470 Series
* Internal Shift Clock Mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External Shift Clock Mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
100
MB90470 Series
(10) I/O Expanded Serial Interface Timing Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name External shift clock mode output pin CL = 80 pF + 1 TTL Internal shift clock mode output pin CL = 80 pF + 1 TTL
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Conditions Value Min 8 tCP - 80 - 120 100 200 tCP 4 tCP 4 tCP 60 120 60 120 Max + 80 + 160 150 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz Remarks
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Notes : * These AC ratings are for operation in CLK synchronous mode. * CL is the load capacitance applied to pins during testing. * tCP : See (1) Clock Timing Ratings. * Values shown are target values. * VCC = VCC3 = VCC5
101
MB90470 Series
* Internal shift clock mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
102
MB90470 Series
(11) I2C Timing Symbol fSCL tBUS tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO Pin name
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Conditions Value Min 0 4.7 4.0 4.7 4.0 4.7 0 40 4.0 Max 100 1000 300 Unit kHz s s s s s s ns ns ns s First clock pulse is generated after this interval. Remarks
Parameter SCL clock frequency Bus free time between stop and start Hold time (resend) start SCL clock "L" status hold time SCL clock "H" status hold time Resend start condition setup time Data hold time Data setup time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time Note : VCC = VCC3 = VCC5
0.8 VCC
SDA
tBUS
0.2 VCC tLOW tR tHIGH tF tHDSTA
0.8 VCC
SCL
0.2 VCC
tHDSTA
tHDDAT fSCL
tSUDAT
tSUSTA
tSUSTO
103
MB90470 Series
(12) Timer Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name TIN0, IN0, IN1, PWC0 to PWC3 Conditions Value Min 4 tCP Max Unit Remarks
Parameter
Symbol tTIWH tTIWL
Input pulse width
ns
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
TIN0, PWC0 to PWC3, IN0, IN1
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(13) Timer Output Timing Symbol tTO
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name TOT0, PPG0 to PPG5, OUT0 to OUT5 Conditions 80 pF load Value Min 30 Max Unit Remarks
Parameter CLK Tout change time PPG0 to PPG5 change time OUT0 to OUT5 change time Note : VCC = Vcc3 = VCC5
ns
CLK
0.7 VCC
TOUT,
PPG0 to PPG5, OUT0 to OUT5
0.7 VCC 0.3 VCC
tTO
104
MB90470 Series
(14) Trigger Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name ADTG, IRQ0 to IRQ7 Conditions Value Min 5 tCP 1 Max Unit ns s Remarks In normal operation Stop mode
Parameter
Symbol tTRGH tTRGL
Input pulse width
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
IRQ0 to IRQ7, ADTG
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
(15) Up/down Counter Timing Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL ZIN0, ZIN1 AIN0, AIN1, BIN0, BIN1
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Conditions Value Min 8 tCP 8 tCP 8 tCP 8 tCP 4 tCP 4 tCP 80 pF load 4 tCP 4 tCP 4 tCP 4 tCP 4 tCP 4 tCP 4 tCP 4 tCP Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter AIN input "H" pulse width AIN input "L" pulse width BIN input "H" pulse width BIN input "L" pulse width AIN BIN time BIN AIN time AIN BIN time BIN AIN time BIN AIN time AIN BIN time BIN AIN time AIN BIN time ZIN input "H" pulse width ZIN input "L" pulse width
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
105
MB90470 Series
tAHL 0.8 VCC 0.8 VCC 0.2 VCC
tALL
AIN
0.2 VCC
tAUBU
tBUAD
tADBD
tBDAU
0.8 VCC
0.8 VCC 0.2 VCC tBHL tBLL 0.2 VCC
BIN
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
BIN
tBUAU
tAUBD
tBDAD
tADBU
0.8 VCC
AIN
0.2 VCC
0.8 VCC
0.8 VCC
ZIN
tZHL tZLL
0.2 VCC
0.2 VCC
106
MB90470 Series
(16) Chip Select Output Timing Symbol tSVRL tSVWL tRHSV tWHSV
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name CS0 to CS3, RD CS0 to CS3, WRH, WRL RD, CS0 to CS3 WRH, WRL, CS0 to CS3 Conditions Value Min tCP / 2 - 10 tCP / 2 - 10 tCP / 2 - 20 tCP / 2 - 20 Max Unit ns ns ns ns Remarks
Parameter Chip select output valid time RD Chip select output valid time WR RD chip select output valid time WR chip select output valid time
Notes : * tCP : See (1) Clock Timing Ratings. * VCC = VCC3 = VCC5
tSVRL 2.4 V
RD
0.8 V tRHSV 2.4 V 0.8 V
A23 to A16, CS0 to CS3
D15 to D00
2.4 V Read data 0.8 V tSVWL tWHSV 2.4 V 0.8 V
WRH, WRL
D15 to D00
Undefined
Write data
Note : The chip select output signal changes at the same time due to the structure of the internal bus, leading to the possibility of a bus fight. AC warranty does not apply between ALE output signals and chip select output signals. 107
MB90470 Series
5. A/D Converter Electrical Characteristics
Parameter Resolution Total error
Symbol Pin name
(VCC = AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Min Typ Max 10 3.0 4.0 2.5 3.0 1.9 2.4
AVSS + 2.5 LSB AVSS + 3.0 LSB
Unit bit LSB
Remarks

at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = 1.8 V to 2.2 V at VCC = AVCC = at VCC = AVCC = 1.8 V to 2.2 V at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = 1.8 V to 2.2 V at AVRH 2.7 V
LSB 1.8 V to 2.2 V LSB LSB
Linear error

Differential linear error

LSB 2.2 V to 3.6 V LSB mV
AVSS - 1.5 LSB
AVSS + 0.5 LSB AVSS + 0.5 LSB
Zero transition voltage
VOT AN0 to AN7
AVSS - 2.0 LSB
mV 1.8 V to 2.2 V mV mV s A V V V mA A A A LSB
AVRH - 3.5 LSB AVRH - 1.5 LSB AVRH + 0.5 LSB
Full scale transition voltage VFST AN0 to AN7
AVRH - 4.0 LSB AVRH - 1.5 LSB AVRH + 1.0 LSB
Conversion time Analog port input current Analog input voltage Reference voltage
IAIN VAIN IA IAH IR IRH
AN0 to AN7 AN0 to AN7
5.8125*1 AVSS AVSS + 2.2
0.1 1.2 95
10 AVRH AVCC AVCC 4.4 5* 5* 4
2
AVRH AVSS + 1.8 AVCC AVCC AVRH AVRH
AN0 to AN7
at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = 1.8 V to 2.2 V
Supply current Reference voltage supply current Inter-channel variation

170
2
*1 : At machine clock frequency 16 MHz. *2 : Current with A/D converter not operating, and CPU in stop mode (VCC = AVCC = AVRH = 3.0 V)
108
MB90470 Series
Notes : * VCC = VCC3 = VCC5 * The relative error increases as |AVRH - AVSS| is reduced. * Observe the following conditions in applying output impedance on the external circuits of the analog input. Output impedance on the external circuit is recommended to be 6 k or less. If external capacitance is used, it is recommended that this be several thousand times the level of internal capacitors in view of the effects of voltage division between the external capacitor and the interior of the chip. * If the output impedance of the external circuits is too high, the analog voltage sampling time may be insufficient. (sampling time = 3.00 s at machine clock frequency 20 MHz) .
< Reference Data > * Analog Input Circuit * Model analog input circuit
Sample and hold circuit Analog input C0 Comparator RON1 RON2 RON3 RON4 C1
RON1 : approx. 5 k RON2 : approx. 617 RON3 : approx. 617 RON4 : approx. 473
C0 : approx. 35 pF C1 : approx. 2 pF
Note : Values shown here are intended as guidelines.
* A/D Operating Frequency Restrictions Supply voltage A/D conversion time [s] 3.6 V AVCC 3.0 V 3.6 V AVCC 2.7 V 2.7 V > AVCC 2.6 V 2.6 V > AVCC 2.5 V 2.5 V > AVCC 2.4 V 2.4 V > AVCC 2.3 V 2.3 V > AVCC 2.2 V 2.2 V > AVCC 2.1 V 2.1 V > AVCC 2.0 V 2.0 V > AVCC 1.9 V 1.9 V > AVCC 1.8 V 4.650 5.813 6.643 7.750 8.455 9.300 11.63 15.50 23.25 46.50 93.00
Machine clock frequency 20 MHz 16 MHz 14 MHz 12 MHz 11 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz 109
MB90470 Series
* Use of the X0/X1, X0A/X1A Pins Use with a crystal oscillator In normal use (VCC = 2 V or higher) Pull-up resistance 1, 2 Damping resistance 1, 2 C1 to C4 Pull-up For all pins, consult regarding X1A resistance 2 manufacturer of oscillator. (Sample operation using VCC = 2 V, Damping f = 5 MHz or less) resistance 2 Pull-up resistance 1 = 5.1 k Pull-up resistance 2 = 510 k Damping resistance 1 = 0 C4 Damping resistance 2 = 39 k C1 = C2 = 22 pF C3 = C4 = 30 pF
Pull-up resistance 1
X1
X0
X0A
Damping resistance 1
C2
C1
C3
* Sample use of external clock input
X0
MB90470 series
OPEN
X1
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Chip erase time Word (16-bit) programming time Erase/Program cycle Data hold time TA = + 25 C VCC = 3.3 V Conditions Value Min 1000 100000 Typ 1 7 16 Max 15 3600 Unit s s s cycle h Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead
110
MB90470 Series
s SAMPLE CHARACTERISTICS
(1) "H" level output voltage (VCC - VOH) - IOH
1.0 0.9 0.8 0.7 VOH (V) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -1 -2 -3 IOH (mA) -4 VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V -5 VOL (V) TA = +25 C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 2 3 IOL (mA) 4 5 TA = +25 C
(2) "L" level output voltage VOL - IOL
VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V
(3) "H" level input voltage/ "L" level input voltage (CMOS input) VIN - VCC
2.5 TA = +25 C
(4) "H" level input voltage/ "L" level input voltage (hysteresis input) VIN - VCC
2.5 TA = +25 C 2.0 VIH
2.0 VIH VIN (V) VIN (V) 1.5 VIL
1.5 VIL 1.0
1.0
0.5
0.5
0.0 2.7
3.0
3.3 VCC (V)
3.6
3.9
0.0 2.7
3.0
3.3 VCC (V)
3.6
3.9
111
MB90470 Series
(5) Supply Current (fcp = internal stroke frequency) * MASK versions ICC - VCC
90 80 70 60 ICC (mA) 50 40 30 20 10 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 fcp = 4 MHz fcp = 2 MHz fcp = 1 MHz 3.9 TA = +25 C 35 fcp = 20 MHz fcp = 16 MHz fcp = 12.5 MHz fcp = 10 MHz ICCS (mA) 30 25 20 15 10 5 0 2.4 2.7 3.0 3.3 3.6 VCC (V) fcp = 4 MHz fcp = 2 MHz fcp = 1 MHz 3.9 fcp = 16 MHz fcp = 12.5 MHz fcp = 10 MHz
ICCS - VCC
TA = +25 C fcp = 20 MHz
ICCH - VCC
2.0 1.8 1.6 1.4 ICCH (A) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 TA = +25 C 40 35 30 TA = +25 C
ICCL - VCC
ICCL (A)
25 20 15 10 5 0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9
ICCT - VCC
5.0 4.5 4.0 3.5 ICCT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 TA = +25 C
112
MB90470 Series
* FLASH versions ICC - VCC
70 60 50 ICC (mA) 40 30 20 10 0 2.4 2.7 3.0 3.3 VCC (V) 3.6 fcp = 4 MHz fcp = 2 MHz 3.9 5 0 2.4 fcp = 4 MHz fcp = 2 MHz 2.7 3.0 3.3 VCC (V) 3.6 3.9 fcp = 10 MHz TA = +25 C 25 fcp = 20 MHz fcp = 16 MHz ICCS (mA) 20 15 10 fcp = 10 MHz
ICCS - VCC
TA = +25 C fcp = 20 MHz fcp = 16 MHz
ICCH - VCC
1.0 0.9 0.8 0.7 ICCH (A) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 0 2.4 2.7 ICCHL (A) TA = +25 C 30 25 20 15 10 5 TA = +25 C
ICCL - VCC
3.0
3.3 VCC (V)
3.6
3.9
ICCT - VCC
5.0 4.5 4.0 3.5 ICCT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 TA = +25 C
(Continued)
113
MB90470 Series
(Continued)
IA - AVCC
3.0 2.5 2.0 IA (mA) 1.5 1.0 0.5 0.0 2.4 IR (mA) TA = +25 C 100 90 80 70 60 50 40 30 20 10 2.7 3.0 3.3 3.6 3.9 0 2.4 2.7 3.0 3.3 3.6 3.9 TA = +25 C
IR - AVCC
AVCC (V)
AVCC (V)
R - VCC
1000 TA = +25 C
R (k)
100
10 2.4
2.7
3.0 VCC (V)
3.3
3.6
3.9
114
MB90470 Series
s ORDERING INFORMATION
Part number MB90473PF MB90474PF MB90477PF MB90478PF MB90F474LPF MB90F474HPF MB90473PFV MB90474PFV MB90477PFV MB90478PFV MB90F474LPFV MB90F474HPFV Package Remarks
100-pin plastic QFP (FPT-100P-M06)
100-pin plastic LQFP (FPT-100P-M05)
115
MB90470 Series
s PACKAGE DIMENSIONS
100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
23.900.40(.941.016)
* 20.000.20(.787.008)
80 51
81
50
0.10(.004) 17.900.40 (.705.016)
*14.000.20 (.551.008)
INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
(Continued)
116
MB90470 Series
(Continued) 100-pin plastic LQFP (FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
16.000.20(.630.008)SQ
*14.000.10(.551.004)SQ
75 51
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) Note : The values in parentheses are reference values.
117
MB90470 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0303 (c) FUJITSU LIMITED Printed in Japan

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